Hi!
I try to use the F2SDRAM0 port on the HPS to move data.
For doing this I use a DMA CONTROLLER configured for transferring word data from the continuous buffer in the DDR to the TXS port of the PCIE Hard IP.
The problem is when I start the transfert, BUSY status goes to 1, indicating that transfert start, but the length register never decrease. DMA CONTROLLER is stuck…
I suspect that the waitrequest signal is held high by F2SDRAM interface.
Does anyone have that kind of issue?
Do I have to put something (like for ARRIA V) in the uboot environement to enable that bridge?
In Cyclone V SoC (does it have the same HPS?) I had to remove the FPGA-SDRAM ports from reset. They are in reset by default.
You can read the meaning of every register in the Arria 10 Handbook and look for some register that is blocking the communications, that I think it will be the same as mine: FPGAPORTRST register.
This is the code I used to remove the reset from these ports:
//SDRAMC beginning address
#define SDRAMC_REGS 0xFFC20000
//Offset of FPGA-to-SDRAMC ports reset register from the beginning of SDRAMC
#define FPGAPORTRST 0x5080
//Remove FPGA-to-SDRAMC ports from reset so FPGA can access SDRAM through them
*((unsigned int *)(SDRAMC_REGS + FPGAPORTRST)) = 0xFFFF;