Error HPS to FPGA communication

Linux Kernel
1

Hello , i’m using an Arria 10 and i created a communication between the HPS and the FPGA,
but while mapping the addresses on linux Angustrom this error came :

[ 37.621008] Unable to handle kernel paging request at virtual0
[ 37.628202] pgd = c0004000
[ 37.630895] [2e799000] *pgd=00000000
[ 37.634468] Internal error: Oops: 5 [#1] SMP ARM
[ 37.639062] Modules linked in: altvipfb2_drv cfbfillrect cfbimgblt cfbcopyard
[ 37.647443] CPU: 0 PID: 0 Comm: swapper/0 Tainted: G W 4.1.33-l1
[ 37.655580] Hardware name: Altera SOCFPGA Arria10
[ 37.660260] task: c0839de8 ti: c0834000 task.ti: c0834000
[ 37.665642] PC is at __queue_work+0x94/0x408
[ 37.669892] LR is at __queue_work+0x94/0x408
[ 37.674142] pc : [] lr : [] psr: 60080193
[ 37.674142] sp : c0835d88 ip : c0835d88 fp : c0835dc4
[ 37.685564] r10: 00000000 r9 : c0834000 r8 : c0836d10
[ 37.690763] r7 : ee0b3400 r6 : 00000002 r5 : 2e799000 r4 : ee218218
[ 37.697256] r3 : ee8a9920 r2 : 00000000 r1 : 00000006 r0 : ee822c00
[ 37.703753] Flags: nZCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment kel
[ 37.711112] Control: 10c5387d Table: 2e3b004a DAC: 00000015
[ 37.716829] Process swapper/0 (pid: 0, stack limit = 0xc0834218)
[ 37.722806] Stack: (0xc0835d88 to 0xc0836000)
[ 37.727143] 5d80: c0831c40 00000000 0000003c 00000001 ee828
[ 37.735282] 5da0: ee218228 00000100 c003c5e8 c089d57c ee218218 c08a6700 c0838
[ 37.743421] 5dc0: c003c60c c003c190 c0835e04 c0835dd8 c007b284 c003c5f4 ee828
[ 37.751560] 5de0: ee218228 00000001 00000002 c003c5e8 ee218218 c0835e20 c0838
[ 37.759698] 5e00: c007b76c c007b240 c0014640 c08a671c c0834000 c05af9c8 c083c
[ 37.767837] 5e20: c0835e20 c0835e20 00000000 c0836084 00000001 c0834000 00000
[ 37.775975] 5e40: c089d2ac 00000282 c0835ebc c0835e58 c002baec c007b5e4 00000
[ 37.784113] 5e60: c086f0e8 00200000 c0836100 ffff9984 0000000a ffffe000 c08a8
[ 37.792252] 5e80: c0836080 c0835e58 00000004 00000002 c006d264 c0831c40 00000
[ 37.800390] 5ea0: 00000001 ee820000 c05af9c8 ef7fcdc0 c0835ed4 c0835ec0 c0020
[ 37.808528] 5ec0: c0831c40 00000000 c0835efc c0835ed8 c0068fbc c002bfbc f0008
[ 37.816666] 5ee0: c0835f20 f0002100 c0836490 c05af9c8 c0835f1c c0835f00 c0008
[ 37.824805] 5f00: c00105dc 60080013 ffffffff c0835f54 c0835f74 c0835f20 c0018
[ 37.832943] 5f20: 00000000 00000000 000373f2 c0023100 c0834000 c08364dc c0830
[ 37.841081] 5f40: c0836490 c05af9c8 ef7fcdc0 c0835f74 c0835f78 c0835f68 c001c
[ 37.849220] 5f60: 60080013 ffffffff c0835f9c c0835f78 c005f390 c00105a0 c06a9
[ 37.857358] 5f80: c082f304 c0835f78 c05a9ef8 ffffffff c0835fac c0835fa0 c05a8
[ 37.865496] 5fa0: c0835ff4 c0835fb0 c07cbcc8 c05a55f4 ffffffff ffffffff c07c0
[ 37.873635] 5fc0: 00000000 c0812668 00000000 c089ffd4 c0836480 c0812664 c083a
[ 37.881773] 5fe0: 414fc091 00000000 00000000 c0835ff8 0000807c c07cb984 00000
[ 37.889925] [] (__queue_work) from [] (delayed_work_time)
[ 37.898243] [] (delayed_work_timer_fn) from [] (call_tim)
[ 37.906731] [] (call_timer_fn) from [] (run_timer_softir)
[ 37.914960] [] (run_timer_softirq) from [] (__do_softirq)
[ 37.923015] [] (__do_softirq) from [] (irq_exit+0x88/0xc)
[ 37.930208] [] (irq_exit) from [] (__handle_domain_irq+0)
[ 37.938006] [] (__handle_domain_irq) from [] (gic_handle)
[ 37.946319] [] (gic_handle_irq) from [] (__irq_svc+0x40/)
[ 37.953764] Exception stack(0xc0835f20 to 0xc0835f68)
[ 37.958793] 5f20: 00000000 00000000 000373f2 c0023100 c0834000 c08364dc c0830
[ 37.966931] 5f40: c0836490 c05af9c8 ef7fcdc0 c0835f74 c0835f78 c0835f68 c001c
[ 37.975067] 5f60: 60080013 ffffffff
[ 37.978545] [] (__irq_svc) from [] (arch_cpu_idle+0x48/0)
[ 37.985914] [] (arch_cpu_idle) from [] (cpu_startup_entr)
[ 37.994146] [] (cpu_startup_entry) from [] (rest_init+0x)
[ 38.001860] [] (rest_init) from [] (start_kernel+0x350/0)
[ 38.009310] Code: e59750c4 e0855003 e1a00004 ebffff5d (e5953000)
[ 38.015377] —[ end trace ff3eb5e3f75b6a91 ]—
[ 38.019973] Kernel panic - not syncing: Fatal exception in interrupt
[ 38.026298] CPU1: stopping
[ 38.029000] CPU: 1 PID: 0 Comm: swapper/1 Tainted: G D W 4.1.33-l1
[ 38.037137] Hardware name: Altera SOCFPGA Arria10
[ 38.041831] [] (unwind_backtrace) from [] (show_stack+0x)
[ 38.049544] [] (show_stack) from [] (dump_stack+0x8c/0xa)
[ 38.056736] [] (dump_stack) from [] (handle_IPI+0x294/0x)
[ 38.064099] [] (handle_IPI) from [] (gic_handle_irq+0x6c)
[ 38.071633] [] (gic_handle_irq) from [] (__irq_svc+0x40/)
[ 38.079078] Exception stack(0xee90ff60 to 0xee90ffa8)
[ 38.084108] ff60: 00000000 00000000 00027fe8 c0023100 ee90e000 c08364dc 10c00
[ 38.092246] ff80: c0836490 c05af9c8 00000000 ee90ffb4 ee90ffb8 ee90ffa8 c001c
[ 38.100382] ffa0: 60070013 ffffffff
[ 38.103858] [] (__irq_svc) from [] (arch_cpu_idle+0x48/0)
[ 38.111222] [] (arch_cpu_idle) from [] (cpu_startup_entr)
[ 38.119450] [] (cpu_startup_entry) from [] (secondary_st)
[ 38.128457] [] (secondary_start_kernel) from [<0000954c>] (0x954c)
[ 38.135473] —[ end Kernel panic - not syncing: Fatal exception in interrupt

anyone has an idea ?

2

Did you place your component base address on a 0x1000 address boundary? If not try that. Make sure your base address (0x1000 boundary) and span are correct for the mmap() call. I can’t think of anything else at the moment as I’ve not had any issues with this other than the address boundary issue.
Cheers!

3

Send the code where you do the mapping and please write the Qsys address of the component you are trying to access and the bridge it is connected (HPS-to-FPGA or Lightweight HPS-to-FPGA)

4

Hello ,

//these are the addresses generated using “sopcinfo”

#define FPGA_ONCHIP_BASE 0xC0000000
#define FPGA_ONCHIP_SPAN 262144
#define FIFO_BASE 0xC0040000
#define FIFO_SPAN 16
#define FIFO_WRITE ((FIFO_write_status_ptr))
#define FIFO_READ ((FIFO_read_status_ptr))
#define FIFO_SEL ((FIFO_sel_write_status_ptr))
#define READ_FIFO_EMPTY (((FIFO_read_status_ptr+1)) & 2 )
#define FIFO_CSRREGS_BASE 0xff200000
#define FIFO_CSRREGS_SPAN 32

// this is the mapping code
void main(){
if(( fd = open( “/dev/mem”, ( O_RDWR | O_SYNC ) ) ) == -1)
{
printf(“access denied or field \n”);
return( 1 );
}

printf(“access have been granted\n”);
h2p_lw_virtual_base = mmap( NULL, FIFO_CSRREGS_SPAN, ( PROT_READ | PROT_WRITE ), MAP_SHARED, fd, FIFO_CSRREGS_BASE);

if( h2p_lw_virtual_base == MAP_FAILED ) {
printf(“failed to MAP virtuell addresses\n”);
close(fd);
return (1);
}

printf(“mapping using LW bridge successful\n”);
FIFO_write_status_ptr = (unsigned int *)(h2p_lw_virtual_base);
FIFO_read_status_ptr = (unsigned int *)(h2p_lw_virtual_base + FIFO_CSRREGS_SPAN);
FIFO_sel_write_status_ptr = (unsigned int *)(h2p_lw_virtual_base + 3 * FIFO_CSRREGS_SPAN);
h2p_virtual_base = mmap( NULL, FIFO_SPAN, ( PROT_READ | PROT_WRITE ), MAP_SHARED, fd, FIFO_BASE);

if( h2p_virtual_base == MAP_FAILED ) {

printf(“fieled to MAP the virtual addresses of h2f bridges \n”);
close(fd);
return(1);
}
FIFO_write_ptr =(unsigned int *)(h2p_virtual_base);
FIFO_read_ptr = (unsigned int *)(h2p_virtual_base + FIFO_SPAN);
FIFO_sel_write_ptr = (unsigned int *)(h2p_virtual_base + FIFO_SPAN + FIFO_SPAN);

}

5

The problems I see are two in principle.
First, if you connected the FPGA component to the HPS through the Lightweight bridge, the addresses are wrong.
The address 0xC0000000 is the beginning of the (non-Lightweight) HPS-to-FPGA bridge.
The Lightweight HPS-to-FPGA bridge starts at 0xFF200000.
To the beginning of the bridge you have to add the address you set in Qsys and that is the phisical address of the component as see by the processor.
I think the error you see in the screen is because you were accessing addresses where no component exists and therefore the answer to the processor is never finished.The processor waits for it and a watchdog in
the OS jumps to free the processor from that wrong hardware access and give you the control back to the console.

Second, the span of a component refers to its size (the adress space chunk reserved for it) in Bytes. It looks strange this line h2p_lw_virtual_base + FIFO_CSRREGS_SPAN. If you add the beginning + the span you are accessing to the address next to the last byte of the component, so you are outside the address range of the
component. The same when you add 3*FIFO_CSRREGS_SPAN.
If the component has a 32-bit (4Byte) bus, you should access it with the following pointers instead:
1st register in the device: reg0 = (unsigned int *)(h2p_lw_virtual_base);
2nd register in the device: reg1 = (unsigned int *)(h2p_lw_virtual_base + 4);
3rd register in the device: reg2 = (unsigned int )(h2p_lw_virtual_base + 24);
4th register in the device: reg2 = (unsigned int )(h2p_lw_virtual_base + 34);
Since the span is 32Byte thats it, 4registers of 4Byte each = 32Byte of span.

Hope it helps.

1 Like
6

Did this solution work ? Having issues running the same tutorial - not getting any errors but also not receiving any output on my FPGA. It seems that my Read FIFO is accurately being populated as my FILL_LEVEL increases and decreases accurately. Yet, I am receiving only zeros upon reading from the FIFO. I am running the same tutorial program as ifarhat and have the same address setup.

7

If you are receiving the output then you must follow some of the guidelines from which you cant retrieve the FPGA for that simply follow the blog of the Epson printer recovery mode by that you can make the change of settings from there.