I have been unable to successfully reprogram the FPGA in the Arria 10 using the device tree overlay. I’m interested in writing a new core.rbf image to the FPGA from Linux. If I don’t include
partial-fpga-config in the DT overlay, then fpga manager fails in drivers/fpga/socfpga-a10.c in socfpga_a10_fpga_write_init, because it appears that only partial reconfiguration is supported:
if (info->flags & FPGA_MGR_PARTIAL_RECONFIG)
cfg_width = CFGWDTH_16;
But if I include
partial-fpga-config in the DT overlay, then it fails in socfpga_a10_fpga_write_complete because socfpga_a10_fpga_wait_for_pr_done returns an error.
Has anyone successfully reconfigured the fpga on Arria 10 using these drivers? I’m not defining actual PRs within my base fpga region; I’m simply interested in reprogramming the core.rbf image to the FPGA from Linux user space, and have thus far been unsuccessful.
I think I’ve answered my own questions here.
First, I believe full reconfiguration is disabled because if you need to do full configuration, then a reboot is required. And if a reboot is required, you might as well just load the new configuration at boot time using the normal u-boot FPGA configuration procedure.
Second, in order to load a core.rbf file using partial reconfiguration, the image needs to be generated (or converted) with the Configuration Scheme (i.e. Mode) set to Passive Parallel x16. The Arria 10 GHRD project defaults to Passive Serial, which is not the mode expected by the fpga-mgs driver.
To get this all to work, I created a Conversion Setup File (.cof) in Quartus to convert my SOF Data file to a RBF file, with Mode set to Passive Parallel x16, Create CvP files checked and Compression checked under the SOF Data File Properties. I could then use the .cof setup file to convert my .sof to periph.rbf and core.rbf, with the core.rbf able to be loaded by the fpga-region/fpga-mgr drivers triggered by loading the device tree overlay.
EDIT: I found that actually marking the “Compression” check mark results in a failure to load. It seems as though the kernel driver for the Arria 10 does not accurately detect that the image is compressed.
We are trying to configure FPGA from Linux-4.1.22-ltsi and we followed the steps as you suggested
- “partial-fpga-config” entry is added in the fpga overlay device tree file.
- Created the RBF file with mode set to Passive Parallel x16 (No Compression)
but we are getting below error while programming
6.330233] fpga_manager fpga0: writing socfpga.rbf to SoCFPGA Arria10 FPGA Manager
[ 37.711715] In socfpga_a10_fpga_write_complete
[ 37.717732] fpga_manager fpga0: Error after writing image data to FPGA
[ 37.725579] failed to load fpga image
[ 37.729235] of_overlay_create: Pre-apply notifier failed (err=-22)
[ 37.735415] create_overlay: Failed to create overlay (err=-22)
We have not refined any PR’s in the FPGA, we wanted to reprogram the FPGA from linux.
Please provide your suggestion for the above problem.
I learned after writing this, that we cannot completely reprogram the A10 FPGA from Linux. The issue is that the DDR controller for the HPS lives in the FPGA, so if we were to reprogram the FPGA from Linux, the DDR controller would be reset and bad things would happen in Linux. If we want to reprogram the FPGA from Linux, we have to partition the FPGA design into regions, and we can only do partial reconfiguration from Linux.