I have created a communication between the hps and fpga for Arria 10, at first i tested 32-bit axi bridge and it worked will and then i tested the 64-bit interface and also it worked will, now i’m testing the 128-bit interface and it does not seem to work.
in fact the design contain 2 FIFO one for data coming from the HPS and one for data going to the HPS.
each time i change the bus (hps2fpga interface) size i change also the fifo data width so that the width is equal to the bus size.
it worked will for 32 and 64-bit bus size, but for the 128-bit the data in the FIFO are not in order and there is some values that are zeros.
does any one have an idea or have used the 128-bit interface that can help me figure out the issue ?