Cyclone V SoC Kit Configuration Headers and Switches

I have the terasic Cyclone V SoCKit here Board . While trying to configure the FPGA, I accidentally uprooted the USB Blaster Port.Now, I wish to use the 10 pin Jtag Header to download a program to the FPGA. I realize that what follows constitutes an extremely newbie question but I haven’t been able to figure it.

From what I have gathered, there are 2 types of setting headers :

    and switches like SWITCH 6 and SWITCH 4 that need to be properly configured.
    From what I understand, Switch 6 represents the MSEL pins and the documentation states that Switch 4 controls “whether the HPS or HSMC connector is included in the JTAG chain via SW4”. I realize that MSEL pins are responsible for selecting the boot mode, but that is all I’ve been able to figure out.
    I want to know what positions to set to these switches and jumpers to enable simple JTAG Programming via the USB Blaster Cable. I have also attached images(can’t attach more than 1) of the headers and their descriptions as per the documentation(SoC Kit User Manual).

Thank you!