DE0 nano SOC - Accessing Ethernet without using HPS


I am playing with the DE0 nano SOC dev board which has a Cyclone V SOC installed. I am pretty comfortable playing with the FPGA but I haven’t used the HPS. I’m new to interfacing the FPGA to the network so I apologize for using poor terminology.

My goal is to be able to receive TCP/IP packets onto my development board, process the information with my FGPA firmware, and then transmit a TCP/IP packet back onto the network. My Cyclone V - SOC chip is interfacing with a “Gigabit Ethernet Transceiver with RGMII” chip (part number: KSZ9031RNX). The problem is that the KSZ9031RNX is interfacing with dedicated HPS pins. My first questions is:

  1. Is there a way to ‘Loan IO’ or permit the FPGA to directly use the EMAC without having to program the SOC ? If yes, how can this be achieved?

  2. Can you recommend any tutorials or projects that do something similar to what I describe above?

  3. Assuming that I have a way to directly interface the FPGA with the KSZ9031RNX chip, can you recommend any examples/tutorials on how I can send or receive packets using a generic gigabit transceiver Module (preferably in VHDL)?

Thank you so much,


DE0 Nano SOC*:

*See sheets 5 and 15 for where the FPGA-SOC chips interfaces with the KSZ9031RNX

I was about to say that I highly doubt is possible to re-route HPS IO to FPGA, but then I found this:

This application note describes the steps required to route an HPS peripheral through the FPGA interface
using Platform Designer (Standard) and Intel®
Prime Standard Edition software. A simple
design example is included to demonstrate exporting HPS EMAC0 and I2C0 peripheral signals to the
FPGA interface using a Cyclone V SoC Development Kit

Good luck! :slight_smile:

Hi Chris,
Thank you so much for posting this. I am excited to read it.
If I figure it out, I plan on posting a response here for future posterity.

Thanks :smiley: