HPS_2_FPGA simulation!

Hello ,

i have created a communication between ARM and FPGA using FIFOs , one for input and one for output, now before testing my design on the board, i want to perform a functional simulation for the project, the problem is that my top level design is based on the GHRD (golden hardware reference design) which contains a lot of signal (see (1)) and i’m not sure on what to do them , all i need is to see if data reaches the input fifo and the output fifo or not,
any advise ?

(1) : this is the top level entity signals
module a10_flat_top (

output reg [3:0] fpga_led_pio,

output wire hps_memory_mem_act_n,
output wire hps_memory_mem_bg,
output wire hps_memory_mem_par,
input wire hps_memory_mem_alert_n,
inout wire [4-1:0] hps_memory_mem_dbi_n,
output wire [16:0] hps_memory_mem_a,
output wire [1:0] hps_memory_mem_ba,
output wire hps_memory_mem_ck,
output wire hps_memory_mem_ck_n,
output wire hps_memory_mem_cke,
output wire hps_memory_mem_cs_n,
output wire hps_memory_mem_reset_n,
inout wire [32-1:0] hps_memory_mem_dq,
inout wire [4-1:0] hps_memory_mem_dqs,
inout wire [4-1:0] hps_memory_mem_dqs_n,
output wire hps_memory_mem_odt,
input wire hps_memory_oct_rzqin,
input wire emif_ref_clk,

input wire hps_uart1_RX,
output wire hps_uart1_TX,
inout wire hps_i2c1_SDA,
inout wire hps_i2c1_SCL,
inout wire hps_sdio_CMD,
output wire hps_sdio_CLK,
inout wire hps_sdio_D0,
inout wire hps_sdio_D1,
inout wire hps_sdio_D2,
inout wire hps_sdio_D3,
inout wire hps_sdio_D4,
inout wire hps_sdio_D5,
inout wire hps_sdio_D6,
inout wire hps_sdio_D7,
inout wire hps_gpio_GPIO14,
inout wire hps_gpio_GPIO05,
inout wire hps_gpio_GPIO16,
inout wire hps_gpio_GPIO17,

input wire fpga_clk_100,
input wire fpga_reset_n

thank you

I think that you can:

  1. The communication interface between HPS and FPGA should be the Avalon Interfaces(MM or ST).

  2. You can wrap your RTL module (FIFO) include an Avalon MM Slave interface.

  3. Simulate from Avalon MM Master to access your FIFO module( with Avalon MM Slave interface).

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