I followed the A10 GSRD v16.1 example (thanks!) to build the reference design successfully. I was also able to add a couple of rams to the reference design for the ARM core to read and write (through AVMM). The problem is when I start to add the IOPLL component in the Qsys (ghrd_10as066n2.qsys), those rams can’t be accessed. Software code, mm_clock_crossing_bridge, clock source, and clock_bridge have been independently checked and are OK. The design is broken only when I start to use IOPLL (e.g. just taking 100Mhz clock to generate another 100Mhz clock). Any suggestions here? (I haven’t added SignalTap to verify the clock yet though). Thanks.