Read Write DDR4 through HPS2FPGA Bridge

1

Hi,

I am working with an Arria 10 with 2 DDR4 memories. One is connected to the HPS EMIF and the other is connected to the HPS2FPGA bridge. However, when I read and write data, some of the read data does not match the return data. For example, I tried writing 0x0 to 0x100 using mmap and read the data, every 16th and 17th data address did not write correctly (0, 1, 16, 17, 32, 33 … etc.). However, the behavior has changed between compiles when I add or remove a PIO (I have not played with much else yet only PIOs). I have had a project that only did not write the first value correctly and would write that value to the 16th address position (I am writing 32 bits at a time). I have also compiled a few times where I can read values, but when I try to write values, Linux will hang and I either need to power cycle or hit the reset button. However, I have had some compiles that work as expected (written values match the read values), but I cannot figure out what causes it to not work when I add or remove QSYS IP. One thing that I am looking into is a ram timing not met message from the Quartus compiler. I cannot remember if I receive that message for the compiles that worked properly. I have not used timequest analyzer before; I am in the learning process.To me it seems like a timing problem so I will try to resolve that first. Any suggestions, comments, or help would be much appreciated.

Thank you

2

Just to tie up this loose end, I solved my problem. It was indeed a timing problem. After changing some synthesis settings in Quartus and changing my architecture in QSYS, the “RAM timing not met” warning message was removed and my system worked as expected.

3

I see this is an old post rsl12398, but I am trying to get into the DDR4 on my Arria 10 board to access the RAM from System Verilog code in the FPGA. I have a Avalon Memory Mapped External Memory Slave Controller instantiated in QSYS and have appropriate pin connections through ports in my top module. I am operating the Avalon slave via registers in my Verilog to try to duplicate the Avalon I/O diagrams I see in the Avalon Interface Specification document (specifically the burst mode writes and reads. I don’t know if this is similar to the road you went down but I am having very patchy progress.

I would like to know more about the approach you took. Did you use the avalon bus for control? Was your control logic from within the FPGA fabric or inside a NIOS processor, or in the HPS? I am using the timing parameters from the DDR4 example project (from QSYS) but do you think this is a problem (since I haven’t changed much it seems they should work). I get ok results from the cal_success interface even though I have not had write - read success yet.

If you have any advice or resources to share it would be much appreciated.