[SOLVED]Multiple ethernet phy on one MDIO


#1

Hello,
On our Arria 10 board we have 3 ethernet ports, connected to MDIO1directly to the HPS. What is the device-tree entry which will allow work for all of them. I tried something like this:
hps_i_emac_emac0: ethernet@0xff800000 {
compatible = “synopsys,dwmac-18.0”, “altr,socfpga-stmmac”, “snps,dwmac-3.72a”, “snps,dwmac”;
reg = <0xff800000 0x00002000>;
interrupt-parent = <&hps_arm_gic_0>;
interrupts = <0 92 4>;
phy-handle = <&phy0>;
clocks = <&l4_mp_clk>; /* appended from boardinfo /
clock-names = “stmmaceth”; /
embeddedsw.dts.params.clock-names type STRING /
interrupt-names = “macirq”; /
embeddedsw.dts.params.interrupt-names type STRING /
rx-fifo-depth = <16384>; /
embeddedsw.dts.params.rx-fifo-depth type NUMBER /
snps,multicast-filter-bins = <256>; /
embeddedsw.dts.params.snps,multicast-filter-bins type NUMBER /
snps,perfect-filter-entries = <128>; /
embeddedsw.dts.params.snps,perfect-filter-entries type NUMBER /
status = “okay”; /
appended from boardinfo /
tx-fifo-depth = <4096>; /
embeddedsw.dts.params.tx-fifo-depth type NUMBER /
address-bits = <48>;
max-frame-size = <1518>;
local-mac-address = [00 00 00 00 00 00];
phy-mode = “rgmii”; /
appended from boardinfo /
/
phy-addr = <0x00000001>; appended from boardinfo /
resets = <&hps_i_rst_mgr_rstmgr 32>; /
appended from boardinfo /
reset-names = “stmmaceth”; /
appended from boardinfo /
altr,sysmgr-syscon = <&hps_i_sys_mgr_core 0x44 0>; /
appended from boardinfo */
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy0@0 {
compatible = “snps,dwmac-mdio”;
reg = <0>;
};
};
}; //end ethernet@0xff800000 (hps_i_emac_emac0)

	hps_i_emac_emac1: ethernet@0xff802000 {
		compatible = "synopsys,dwmac-18.0", "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
		reg = <0xff802000 0x00002000>;
		interrupt-parent = <&hps_arm_gic_0>;
		interrupts = <0 93 4>;
		phy-handle = <&phy1>;
		clocks = <&l4_mp_clk>;	/* appended from boardinfo */
		clock-names = "stmmaceth";	/* embeddedsw.dts.params.clock-names type STRING */
		interrupt-names = "macirq";	/* embeddedsw.dts.params.interrupt-names type STRING */
		rx-fifo-depth = <16384>;	/* embeddedsw.dts.params.rx-fifo-depth type NUMBER */
		snps,multicast-filter-bins = <256>;	/* embeddedsw.dts.params.snps,multicast-filter-bins type NUMBER */
		snps,perfect-filter-entries = <128>;	/* embeddedsw.dts.params.snps,perfect-filter-entries type NUMBER */
		status = "okay";	/* embeddedsw.dts.params.status type STRING */
		tx-fifo-depth = <4096>;	/* embeddedsw.dts.params.tx-fifo-depth type NUMBER */
		address-bits = <48>;
		max-frame-size = <1518>;
		local-mac-address = [00 00 00 00 00 00];
		phy-mode = "rgmii";	/* appended from boardinfo */

/* phy-addr = <0x00000002>; appended from boardinfo /
resets = <&hps_i_rst_mgr_rstmgr 33>; /
appended from boardinfo /
reset-names = “stmmaceth”; /
appended from boardinfo /
altr,sysmgr-syscon = <&hps_i_sys_mgr_core 0x48 0>; /
appended from boardinfo */
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy1: ethernet-phy1@1 {
compatible = “snps,dwmac-mdio”;
reg = <1>;
};
};
}; //end ethernet@0xff802000 (hps_i_emac_emac1)

	hps_i_emac_emac2: ethernet@0xff804000 {
		compatible = "synopsys,dwmac-18.0", "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
		reg = <0xff804000 0x00002000>;
		interrupt-parent = <&hps_arm_gic_0>;
		interrupts = <0 94 4>;
		phy-handle = <&phy2>;
		clocks = <&l4_mp_clk>;	/* appended from boardinfo */
		clock-names = "stmmaceth";	/* embeddedsw.dts.params.clock-names type STRING */
		interrupt-names = "macirq";	/* embeddedsw.dts.params.interrupt-names type STRING */
		rx-fifo-depth = <16384>;	/* embeddedsw.dts.params.rx-fifo-depth type NUMBER */
		snps,multicast-filter-bins = <256>;	/* embeddedsw.dts.params.snps,multicast-filter-bins type NUMBER */
		snps,perfect-filter-entries = <128>;	/* embeddedsw.dts.params.snps,perfect-filter-entries type NUMBER */
		status = "okay";	/* appended from boardinfo */
		tx-fifo-depth = <4096>;	/* embeddedsw.dts.params.tx-fifo-depth type NUMBER */
		address-bits = <48>;
		max-frame-size = <1518>;
		local-mac-address = [00 00 00 00 00 00];
		phy-mode = "rgmii";	/* appended from boardinfo */

/* phy-addr = <0x00000003>; appended from boardinfo /
resets = <&hps_i_rst_mgr_rstmgr 34>; /
appended from boardinfo /
reset-names = “stmmaceth”; /
appended from boardinfo /
altr,sysmgr-syscon = <&hps_i_sys_mgr_core 0x4C 0>; /
appended from boardinfo */
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy2: ethernet-phy2@2 {
compatible = “snps,dwmac-mdio”;
reg = <2>;
};
};
}; //end ethernet@0xff804000 (hps_i_emac_emac2)
But I always get:
socfpga-dwmac ff800000.ethernet: no reset control found
socfpga-dwmac ff804000.ethernet: no reset control found
Another error messages are also present.
Do I need to add something in reset controller node?
Do I need to remove CONFIG_FIXED_PHY?..

Any suggestions?

Cordially,
Georgi


#2

Solved! The missed link was aliases section in dts file.
aliases {

ethernet0 = “/sopc@0/ethernet@0xff800000”;
ethernet1 = “/sopc@0/ethernet@0xff802000”;
ethernet2 = “/sopc@0/ethernet@0xff804000”;

}; //end aliases
hps_i_emac_emac0: ethernet@0xff800000 {
compatible = “synopsys,dwmac-18.0”, “altr,socfpga-stmmac”, “snps,dwmac-3.72a”, “snps,dwmac”;
reg = <0xff800000 0x00002000>;
interrupt-parent = <&hps_arm_gic_0>;
interrupts = <0 92 4>;
clocks = <&l4_mp_clk>; /* appended from boardinfo /
clock-names = “stmmaceth”; /
embeddedsw.dts.params.clock-names type STRING /
interrupt-names = “macirq”; /
embeddedsw.dts.params.interrupt-names type STRING /
rx-fifo-depth = <16384>; /
embeddedsw.dts.params.rx-fifo-depth type NUMBER /
snps,multicast-filter-bins = <256>; /
embeddedsw.dts.params.snps,multicast-filter-bins type NUMBER /
snps,perfect-filter-entries = <128>; /
embeddedsw.dts.params.snps,perfect-filter-entries type NUMBER /
status = “okay”; /
embeddedsw.dts.params.status type STRING /
tx-fifo-depth = <4096>; /
embeddedsw.dts.params.tx-fifo-depth type NUMBER /
address-bits = <48>;
max-frame-size = <1518>;
local-mac-address = [00 00 00 00 00 00];
altr,sysmgr-syscon = <&hps_i_sys_mgr_core 0x44 0>; /
appended from boardinfo */
resets = <&hps_i_rst_mgr_rstmgr 32>;
phy-handle = <&phy1>;
phy-mode = “rgmii”;
}; //end ethernet@0xff800000 (hps_i_emac_emac0)

	hps_i_emac_emac1: ethernet@0xff802000 {
		compatible = "synopsys,dwmac-18.0", "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
		reg = <0xff802000 0x00002000>;
		interrupt-parent = <&hps_arm_gic_0>;
		interrupts = <0 93 4>;
		clocks = <&l4_mp_clk>;	/* appended from boardinfo */
		clock-names = "stmmaceth";	/* embeddedsw.dts.params.clock-names type STRING */
		interrupt-names = "macirq";	/* embeddedsw.dts.params.interrupt-names type STRING */
		rx-fifo-depth = <16384>;	/* embeddedsw.dts.params.rx-fifo-depth type NUMBER */
		snps,multicast-filter-bins = <256>;	/* embeddedsw.dts.params.snps,multicast-filter-bins type NUMBER */
		snps,perfect-filter-entries = <128>;	/* embeddedsw.dts.params.snps,perfect-filter-entries type NUMBER */
		status = "okay";	/* embeddedsw.dts.params.status type STRING */
		tx-fifo-depth = <4096>;	/* embeddedsw.dts.params.tx-fifo-depth type NUMBER */
		address-bits = <48>;
		max-frame-size = <1518>;
		local-mac-address = [00 00 00 00 00 00];
		phy-mode = "rgmii";	/* appended from boardinfo */
		resets = <&hps_i_rst_mgr_rstmgr 33>;	/* appended from boardinfo */
		reset-names = "stmmaceth";	/* appended from boardinfo */
		altr,sysmgr-syscon = <&hps_i_sys_mgr_core 0x48 0>;	/* appended from boardinfo */
		phy-handle = <&phy2>;

		mdio1 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dwmac-mdio";

			phy1: ethernet-phy1@1 {
				reg = <1>;
			};
			phy2: ethernet-phy2@2 {
				reg = <2>;
			};
			phy3: ethernet-phy3@3 {
				reg = <3>;
			};
		};
	}; //end ethernet@0xff802000 (hps_i_emac_emac1)

	hps_i_emac_emac2: ethernet@0xff804000 {
		compatible = "synopsys,dwmac-18.0", "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
		reg = <0xff804000 0x00002000>;
		interrupt-parent = <&hps_arm_gic_0>;
		interrupts = <0 94 4>;
		clocks = <&l4_mp_clk>;	/* appended from boardinfo */
		clock-names = "stmmaceth";	/* embeddedsw.dts.params.clock-names type STRING */
		interrupt-names = "macirq";	/* embeddedsw.dts.params.interrupt-names type STRING */
		rx-fifo-depth = <16384>;	/* embeddedsw.dts.params.rx-fifo-depth type NUMBER */
		snps,multicast-filter-bins = <256>;	/* embeddedsw.dts.params.snps,multicast-filter-bins type NUMBER */
		snps,perfect-filter-entries = <128>;	/* embeddedsw.dts.params.snps,perfect-filter-entries type NUMBER */
		status = "okay";	/* embeddedsw.dts.params.status type STRING */
		tx-fifo-depth = <4096>;	/* embeddedsw.dts.params.tx-fifo-depth type NUMBER */
		address-bits = <48>;
		max-frame-size = <1518>;
		local-mac-address = [00 00 00 00 00 00];
		altr,sysmgr-syscon = <&hps_i_sys_mgr_core 0x4C 0>;	/* appended from boardinfo */
		resets = <&hps_i_rst_mgr_rstmgr 34>;
		phy-handle = <&phy3>;
		phy-mode = "rgmii";
	}; //end ethernet@0xff804000 (hps_i_emac_emac2)