Sopc2dts, what means "Transparent bridge not yet supported"?


Dear reader,

Tl;dr: Does anybody know what the “Transparent bridge fifo_65_0 of type altera_avalon_fifo not yet supported.” means and how it could be fixed?

I am trying to generate and dts file of my qsys system. It consists out of a HPS, a custom IP, 2 FIFO’s, and some other components. I try to use the FIFO’s to store data between my custom IP and the HPS. It all compiles without any problems. However when I try to generate a dts file via sopc2dts

sopc2dts --input soc_system.sopcinfo --output soc_system.dts --type dts --bridge-removal all --clocks

I get the following mesages back:

Transparent bridge in fifo_65_0 of type altera_avalon_fifo is not yet supported.
Transparent bridge in fifo_57_0 of type altera_avalon_fifo is not yet supported.

I already tried to use only a design with a clock source and a FIFO and ran the sopc2dts file with minimal arguments (sopc2dts --input fifo_tryout.sopcinfo --output soc_system.dts --type dts), but this very simplistic setup already results in the given message.

Although the sopc2dts command does output a file, it seems that the FIFO’s (and also my custom ip, which is connected to the FIFO’s) are not included. Therefore I suspect this message/notice results in absence of the FIFO’s and possibly the absence of my custom ip in the output file. Therefore I am trying to fix this problem, but days of work has not yet resulted in a solution.

Does anybody knows what this message means? And how it could (possibly) be fixed?

I am using Quartus Prime 17.1 build 590 and sopc2dts version 17.1 [9b3346002ac555f36b80b1bc56dad1cb86298234]

Thanks in advance :slight_smile:

Kind regards,


I found my solution! I Assumed that my Custom IP and a PLL in my Qsys design didn’t end-up in the DTS due to this messages. However I realized this morning that this is the case due to that the HPS is not connected to my custom IP and the PLL xD According to, you could safely ignore this message, so I am going to do that!


Hi wobbert,
I have the same problem like you:
Transparent bridge in fifo_FPGA_to_HPS of type altera_avalon_fifo is not yet supported.
Transparent bridge in fifo_HPS_to_FPGA of type altera_avalon_fifo is not yet supported.

The communication HPS to FPGA work done, (without FIFO).
The problem is, when I trying to implement two FIFO’s (for permanent communication between FPGA and HPS) . This example doesn’t work for me and i have no idea why? Can you help me, to implement the FIFO’s.
I use the OnChip-RAM and then put the data to HPS…so the plan…


Dear Omicron8,
As stated in my post of December 17th, in my case I could safely ignore the error messages. If you have not yet tried to do so, please give it a try. Otherwise I don’t think I can give you any form of assistance since I have very limited knowledge of this topic. Hope this helps you.