Well. In the interest of pressing on, we created this patch for our company’s A10 SOM (link below). It provides an option to force the SPL to reload the FPGA if it is fully configured (e.g., from any reset condition after it was fully programmed) or if it is completely unprogrammed (no peripheral image loaded). This will only work for designs using split RBF programming where only the peripheral image is specified to be loaded by the SPL. Using a full RBF by the SPL (not desirable, takes too long anyway) will cause the system to loop indefinitely. It seems to work, but YMMV. A better approach would be to create a flag in the ITB block and handle that appropriately, but in the interest of time and our use case this is what we did.
-Mike