Topic Replies Activity
Welcome to the RocketBoards Forum 2 May 18, 2015
Ethernet not working after reboot 1 August 18, 2019
Boot kernel with kexec on socfpga 5 August 14, 2019
Linux Booting stuck at STARTING LIGHTTPD WEBSERVER 5 August 16, 2019
Uboot printf erroe 3 August 16, 2019
A10 Boot from FPGA (SD-Card / Shared-IO) 2 August 14, 2019
U-Boot Make target Error 8 August 13, 2019
HPS writing to its DDR3 SDRAM 1 August 12, 2019
Actual Avalon Address width for HPS SDRAM 1 August 12, 2019
Make_sdimage.py - Error: Failed to copy [Solved] 3 August 10, 2019
Demo Project for FPGA to SDRAM 1 August 9, 2019
Connmanctl and sftp-server are missing from the root fs in the 2018.10 sdimage for the Cyclone V SoC 7 August 8, 2019
Alternate driver for Avalon-MM DMA for PCIe 1 August 8, 2019
Make Error Building Kernel and U-Boot Separately From Git Trees 7 August 6, 2019
U-Boot build in Arria 10(custom board) 1 August 6, 2019
Suggestion for my Project 1 August 5, 2019
Shifed binary image produced by arm-none-eabi-objcopy 1 August 2, 2019
Altera PCIe driver issue with SSD devices 5 July 29, 2019
Unable to boot correct code from QSPI flash 3 July 29, 2019
[solved] Arria 10 HPS OpenCL Compile problem, no hps_isw_handoff folder 2 July 29, 2019
Cycle V not booting up 4 July 25, 2019
About Altera 16550 soft ip driver 1 July 23, 2019
NIOS II and Ethernet 1 July 23, 2019
Looking for I2C slave driver example with Cyclone V SoC I2C controller 3 July 23, 2019
How to see Transceiver received data on UART Terminal 10 July 20, 2019
Not able to compile angstrom kernel for Arrow CycloneV board, has anyone been able to compile for Arrow board? 2 July 17, 2019
Makefile error: hwlib.h no such file or directory 8 July 17, 2019
DE0-Nano-soc/Atlas kit default image.img U-boot loops 5 July 16, 2019
SDRAM calibration error Stratix 10 SoC 1 July 10, 2019
Clock Network Selection Example for Cyclone V 1 July 10, 2019