Yes, except that hardware changes in the FPGA aren’t really transparent to the software since you still need to run ‘sopc-create-header-files’ to extract the mapping to the FPGA resources when anything in the FPGA changes. That isn’t a big problem but the hardware to software connection still requires both paths to work right. Device tree documentation is a bit sketchy to me but I guess Altera is more centered on their FPGAs so they cover that part better than the .dtb implementation.
Hi Jambie,
i try to implement your Project-“CycloneV HPS FIFO” on the DE0 SoC board. The memory mapping from the c-file works, but when i try to send data over the lw_hps to the fpga(HPS_to_FPGA fifo), then hags the Linux completely… My (first)question is, how start you the FPGA? Did you boot the “fpga_system”.rbf with the OS, or you flash first the FPGA and than boot the OS from the SD card?
The short answer is I boot my project .RBF file from the SDcard by placing it where it will be flashed into the FPGA during system startup. You should also be able to program the FPGA after Linux is booted using the Quartus ‘Programmer’ item in the Tools menu. As I recall on my system the Linux will continue to operate after reprogramming the FPGA using the Quartus ‘Programmer’ (though it is not set up right now so I will verify that leter - but I loaded a lot of new versions during development and this is how I recall working).
To install the .RBF file on the SDcard so it boots your project file during startup you can do this. On the Cyclone V board (a DE-1 from Terasic) I normally convert the .sof file produced by the Quartus compile to a .rbf file using the File menu item named ‘Convert Programming Files’. Select .rbf file type, select ‘PPx16’ type, select your .sof file and give the .rbf file a name that is meaningful to your project.
Then copy the .rbf file onto the SDcard. I could not use an Ethernet connection due to company network restrictions so I copied the .rbf file onto a thumb-drive and copied it into my /root directory. The boot directory on the SDcard (assuming you are using Ubuntu and the default SDcard setup from the Terasic website) is in /media/root/5459-A1D621 , and the last part of that directory (the 5459-A1D621) changes when the card is rebuilt or removed without being dismounted, so just locate the latest directory under /media/root. In that directory you will find (at least on my system) the .RBF file that is loaded at startup, it should be named soc_system.rbf. Change directory to this partition on the SDcard by entering ‘cd /media/root/5459-A1D621’ (or whatever the latest name is). Save a copy of the soc_system.rbf file (so you can put it back later if you want to switch back) by copying it to a safe name, for example ‘cp soc_system.rbf ORGsoc_system.rbf’ If you copy your project .RBF file (for example myProject.rbf) into this directory you can now copy your .RBF file over the default file so your’s is the one that is loaded during startup by entering the command ‘cp myProject.rbf soc_system.rbf’ Now if you reboot your project’s .RBF file will be loaded during startup.
I found that as long as you are not adding new hardware interfaces you should not need to recompile anything else (so you can leave your device tree and Linux files as they were and skip re-running uboot) and just rename the .rbf files as described above.
I said earlier that under Ubuntu I reprogrammed the FPGA and continued to use Linux, but I may be remembering that incorrectly (it has been a while since I did a lot of work on the DE-1 board). On the Arria 10 board I definitely reprogram and continue using the same Linux session, but configuration is a bit different there. In any case you would not be able to use the Quartus programmer, then re-start the DE-1 board and see your program since during startup it loads the soc-system.rbf file. I would expect the Linux FIFO programs to hang if run without the .RBF file that operates with them so I believe you are correct that you are not getting your program set in the FPGA as you need. The method described above should work for you.
I will take another look at the instructions in the project. I may have left out some important steps if this was not explained.
Good Luck with it!
Jambie
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@Jambie
I want to see the quartus project files of your upload but somehow the link on filedropper is not working. Can you please share it again. I really need help. I am stuck on how to see data from FPGA onto my putty terminal. I shall highly appreciate your help.
Yes, I’ll get it uploaded again. It is inconvenient that the RocketBoards site does not store the project files, so we have to find other places then link to those.
@Jambie
Thank you so much. Thats so nice of you.
Yea, it is kind of upset that Rocketboard site doesn’t store the project file. But I am also thankful to you for your support and help. Will you please share the link of the upload?
I gave up on FileDropper, it looks like their business is coming to an end. I reduced the size of the Quartus project by removing the temporary and compiled files. This allows it to fit in the space Github allows. I also include the .SOF file so you can program the FPGA without having to go through build, which is good for thiose who just want to try it out first to see if the project has what they are looking for.
Good luck with your programming!