HPS-FPGA DDR sharing on Cyclone V SoC

Hi roberbot,
I’m back working on transfering data between FPGA and HPS. I don’t know a lot about linux kernels and modules, because I worked mainly with FPGA (not SoC until now) firmware. I have probably a trivial question, but I ask you anyway. In your projects you use a module to manage the HPS DMA in order to move data from FPGA to SDRAM and back. Is it possible to move data only with FPGA DMA? I try to explain better what I mean. My idea was to move data from FPGA on-chip RAM to SDRAM through FPGA DMA that use the fpga2hps_sdram interface to write directly in the SDRAM. This because the SDRAM controller of the Cyclone V SoC have a multiport front-end that interface directly with FPGA (precisely the fpga2hps_sdram interface). In your examples, a L3 Interconnect was used to move data together with hps2fpga and fpga2hps bridges, but I would like to use the fpga2hps_sdram interface to have (I hope so) the best throughput and avoid using the HPS cache.
Thanks a lot.
Regards.