HWLIB example design is not running on my custom Board

Hi All,

I have tried to run Altera-SoCFPGA-HardwareLib-FPGA-CV-GNU example design on my custom board (SoC device 5CSEMA2U23I7N). but it didn’t work. Can any one help?

I have tried below steps:

  1. Recompiled Altera Cyclone V GHRD project for my own FPGA device. My board is having only QSPI and DDR3 peripherals on HPS side but I have kept all HPS peripheral selected in GHRD, no modification in Pin Mux page.

  2. Generated a custom preloader with Semihosting and Hardware_Diagnostic Enabled and selected QSPI Flash as boot source. Preloader runs properly. Here is the snapshot:

U-Boot SPL 2013.01.01 (Sep 01 2015 - 16:35:50)
BOARD : Altera SOCFPGA Cyclone V Board
CLOCK: EOSC1 clock 25000 KHz
CLOCK: EOSC2 clock 25000 KHz
CLOCK: F2S_SDR_REF clock 0 KHz
CLOCK: F2S_PER_REF clock 0 KHz
CLOCK: MPU clock 800 MHz
CLOCK: DDR clock 400 MHz
CLOCK: UART clock 100000 KHz
CLOCK: MMC clock 50000 KHz
CLOCK: QSPI clock 400000 KHz
RESET: COLD
INFO : Watchdog enabled
SDRAM: Initializing MMR registers
SDRAM: Calibrating PHY
SEQ.C: Preparing to start memory calibration
SEQ.C: DQS Enable ; Group 0 ; Rank 0 ; Start VFIFO 6 ; Phase 5 ; Delay 13
SEQ.C: DQS Enable ; Group 0 ; Rank 0 ; End VFIFO 7 ; Phase 4 ; Delay 6
SEQ.C: DQS Enable ; Group 0 ; Rank 0 ; Center VFIFO 7 ; Phase 0 ; Delay 10
SEQ.C: Read Deskew ; DQ 0 ; Rank 0 ; Left edge 21 ; Right edge 26 ; DQ delay 3 ; DQS delay 9
SEQ.C: Read Deskew ; DQ 1 ; Rank 0 ; Left edge 19 ; Right edge 27 ; DQ delay 1 ; DQS delay 9
SEQ.C: Read Deskew ; DQ 2 ; Rank 0 ; Left edge 16 ; Right edge 27 ; DQ delay 0 ; DQS delay 9
SEQ.C: Read Deskew ; DQ 3 ; Rank 0 ; Left edge 18 ; Right edge 27 ; DQ delay 1 ; DQS delay 9
SEQ.C: Read Deskew ; DQ 4 ; Rank 0 ; Left edge 22 ; Right edge 25 ; DQ delay 4 ; DQS delay 9
SEQ.C: Read Deskew ; DQ 5 ; Rank 0 ; Left edge 19 ; Right edge 27 ; DQ delay 1 ; DQS delay 9
SEQ.C: Read Deskew ; DQ 6 ; Rank 0 ; Left edge 16 ; Right edge 27 ; DQ delay 0 ; DQS delay 9
SEQ.C: Read Deskew ; DQ 7 ; Rank 0 ; Left edge 20 ; Right edge 27 ; DQ delay 2 ; DQS delay 9
SEQ.C: Write Deskew ; DQ 0 ; Rank 0 ; Left edge 31 ; Right edge 13 ; DQ delay 9 ; DQS delay 4
SEQ.C: Write Deskew ; DQ 1 ; Rank 0 ; Left edge 31 ; Right edge 13 ; DQ delay 9 ; DQS delay 4
SEQ.C: Write Deskew ; DQ 2 ; Rank 0 ; Left edge 25 ; Right edge 19 ; DQ delay 3 ; DQS delay 4
SEQ.C: Write Deskew ; DQ 3 ; Rank 0 ; Left edge 28 ; Right edge 15 ; DQ delay 6 ; DQS delay 4
SEQ.C: Write Deskew ; DQ 4 ; Rank 0 ; Left edge 31 ; Right edge 12 ; DQ delay 9 ; DQS delay 4
SEQ.C: Write Deskew ; DQ 5 ; Rank 0 ; Left edge 31 ; Right edge 13 ; DQ delay 9 ; DQS delay 4
SEQ.C: Write Deskew ; DQ 6 ; Rank 0 ; Left edge 26 ; Right edge 18 ; DQ delay 4 ; DQS delay 4
SEQ.C: Write Deskew ; DQ 7 ; Rank 0 ; Left edge 28 ; Right edge 15 ; DQ delay 6 ; DQS delay 4
SEQ.C: DM Deskew ; Group 0 ; Left edge 27; Right edge 16; DM delay 5
SEQ.C: Read after Write ; DQ 0 ; Rank 0 ; Left edge 26 ; Right edge 21 ; DQ delay 3 ; DQS delay 10
SEQ.C: Read after Write ; DQ 1 ; Rank 0 ; Left edge 24 ; Right edge 22 ; DQ delay 2 ; DQS delay 10
SEQ.C: Read after Write ; DQ 2 ; Rank 0 ; Left edge 21 ; Right edge 22 ; DQ delay 0 ; DQS delay 10
SEQ.C: Read after Write ; DQ 3 ; Rank 0 ; Left edge 22 ; Right edge 22 ; DQ delay 1 ; DQS delay 10
SEQ.C: Read after Write ; DQ 4 ; Rank 0 ; Left edge 26 ; Right edge 19 ; DQ delay 4 ; DQS delay 10
SEQ.C: Read after Write ; DQ 5 ; Rank 0 ; Left edge 24 ; Right edge 21 ; DQ delay 2 ; DQS delay 10
SEQ.C: Read after Write ; DQ 6 ; Rank 0 ; Left edge 20 ; Right edge 22 ; DQ delay 0 ; DQS delay 10
SEQ.C: Read after Write ; DQ 7 ; Rank 0 ; Left edge 24 ; Right edge 22 ; DQ delay 2 ; DQS delay 10
SEQ.C: DQS Enable ; Group 1 ; Rank 0 ; Start VFIFO 6 ; Phase 4 ; Delay 10
SEQ.C: DQS Enable ; Group 1 ; Rank 0 ; End VFIFO 7 ; Phase 4 ; Delay 3
SEQ.C: DQS Enable ; Group 1 ; Rank 0 ; Center VFIFO 7 ; Phase 0 ; Delay 7
SEQ.C: Read Deskew ; DQ 8 ; Rank 0 ; Left edge 22 ; Right edge 25 ; DQ delay 3 ; DQS delay 9
SEQ.C: Read Deskew ; DQ 9 ; Rank 0 ; Left edge 17 ; Right edge 27 ; DQ delay 0 ; DQS delay 9
SEQ.C: Read Deskew ; DQ 10 ; Rank 0 ; Left edge 17 ; Right edge 27 ; DQ delay 0 ; DQS delay 9
SEQ.C: Read Deskew ; DQ 11 ; Rank 0 ; Left edge 17 ; Right edge 27 ; DQ delay 0 ; DQS delay 9
SEQ.C: Read Deskew ; DQ 12 ; Rank 0 ; Left edge 21 ; Right edge 25 ; DQ delay 3 ; DQS delay 9
SEQ.C: Read Deskew ; DQ 13 ; Rank 0 ; Left edge 17 ; Right edge 27 ; DQ delay 0 ; DQS delay 9
SEQ.C: Read Deskew ; DQ 14 ; Rank 0 ; Left edge 18 ; Right edge 27 ; DQ delay 0 ; DQS delay 9
SEQ.C: Read Deskew ; DQ 15 ; Rank 0 ; Left edge 18 ; Right edge 27 ; DQ delay 0 ; DQS delay 9
SEQ.C: Write Deskew ; DQ 8 ; Rank 0 ; Left edge 31 ; Right edge 14 ; DQ delay 8 ; DQS delay 4
SEQ.C: Write Deskew ; DQ 9 ; Rank 0 ; Left edge 30 ; Right edge 15 ; DQ delay 7 ; DQS delay 4
SEQ.C: Write Deskew ; DQ 10 ; Rank 0 ; Left edge 26 ; Right edge 18 ; DQ delay 4 ; DQS delay 4
SEQ.C: Write Deskew ; DQ 11 ; Rank 0 ; Left edge 25 ; Right edge 19 ; DQ delay 3 ; DQS delay 4
SEQ.C: Write Deskew ; DQ 12 ; Rank 0 ; Left edge 31 ; Right edge 14 ; DQ delay 8 ; DQS delay 4
SEQ.C: Write Deskew ; DQ 13 ; Rank 0 ; Left edge 28 ; Right edge 16 ; DQ delay 6 ; DQS delay 4
SEQ.C: Write Deskew ; DQ 14 ; Rank 0 ; Left edge 27 ; Right edge 19 ; DQ delay 4 ; DQS delay 4
SEQ.C: Write Deskew ; DQ 15 ; Rank 0 ; Left edge 27 ; Right edge 18 ; DQ delay 4 ; DQS delay 4
SEQ.C: DM Deskew ; Group 1 ; Left edge 25; Right edge 21; DM delay 2
SEQ.C: Read after Write ; DQ 8 ; Rank 0 ; Left edge 25 ; Right edge 20 ; DQ delay 3 ; DQS delay 10
SEQ.C: Read after Write ; DQ 9 ; Rank 0 ; Left edge 22 ; Right edge 22 ; DQ delay 1 ; DQS delay 10
SEQ.C: Read after Write ; DQ 10 ; Rank 0 ; Left edge 20 ; Right edge 22 ; DQ delay 0 ; DQS delay 10
SEQ.C: Read after Write ; DQ 11 ; Rank 0 ; Left edge 21 ; Right edge 22 ; DQ delay 0 ; DQS delay 10
SEQ.C: Read after Write ; DQ 12 ; Rank 0 ; Left edge 25 ; Right edge 20 ; DQ delay 3 ; DQS delay 10
SEQ.C: Read after Write ; DQ 13 ; Rank 0 ; Left edge 22 ; Right edge 22 ; DQ delay 1 ; DQS delay 10
SEQ.C: Read after Write ; DQ 14 ; Rank 0 ; Left edge 22 ; Right edge 22 ; DQ delay 1 ; DQS delay 10
SEQ.C: Read after Write ; DQ 15 ; Rank 0 ; Left edge 22 ; Right edge 22 ; DQ delay 1 ; DQS delay 10
SEQ.C: LFIFO Calibration ; PHY Read Latency 11
SEQ.C: CALIBRATION PASSED
SEQ.C: Calibration Summary
SEQ.C: Calibration Passed
SEQ.C: FOM IN = 42
SEQ.C: FOM OUT = 43
SDRAM: 512 MiB
SDRAM: Ensuring specified SDRAM size is correct …passed
SDRAM: Running EMIF Diagnostic Test …passed

  1. Imported Altera-SoCFPGA-HardwareLib-FPGA-CV-GNU SW example in my workspace and modify the make file to access my custom preloader. SW design compiles successfully and u-boot-spl.axf and hwlib.axf files generated.

  2. While debugging the SW design Debugger throws below error message in Error Log:

“Target is running, cannot access”

Here is the snapshot of Commands Window:

Connected to running target Altera - Cyclone V SoC (Dual Core) on TCP:localhost
source /v “C:\altera\15.0\embedded\ds-5\sw\debugger\configdb\Scripts\altera_target_check.py”
+print &$Peripherals::$rstmgr::$rstmgr_brgmodrst
$1 = (unsigned int*) P:0xFFD0501C
Cannot access FPGA to check SYS ID registers, expected values are:
Expected value of Peripherals::altera_avalon_sysid_sysid_qsys_control_slave::altera_avalon_sysid_sysid_qsys_control_slave_ID:
0xacd51500/0xffffffff
Expected value of Peripherals::altera_avalon_sysid_sysid_qsys_control_slave::altera_avalon_sysid_sysid_qsys_control_slave_TIMESTAMP:
0x55dd689e/0xffffffff
cd "E:\crl_ddr3_issue\cv_soc_devkit_ghrd_15.0\hps_workspace\Altera-SoCFPGA-HardwareLib-FPGA-CV-GNU"
Working directory "E:\crl_ddr3_issue\cv_soc_devkit_ghrd_15.0\hps_workspace\Altera-SoCFPGA-HardwareLib-FPGA-CV-GNU"
source /v “E:\crl_ddr3_issue\cv_soc_devkit_ghrd_15.0\hps_workspace\Altera-SoCFPGA-HardwareLib-FPGA-CV-GNU\debug-hosted.ds”
+reset system
+wait 30s
Target has been reset
Execution stopped due to a breakpoint or watchpoint: S:0x00000000
S:0x00000000 LDR pc,[pc,#24] ; [0x20] = 0xA8
+stop
WARNING(CMD315): Target is not running
+wait 30s
+set semihosting enabled false
+loadfile “$sdir/u-boot-spl.axf” 0x0
Loaded section .text: S:0xFFFF0000 ~ S:0xFFFF690B (size 0x690C)
Loaded section .rodata: S:0xFFFF690C ~ S:0xFFFF84DA (size 0x1BCF)
Loaded section .data: S:0xFFFF84E0 ~ S:0xFFFF93B3 (size 0xED4)
Entry point S:0xFFFF0000
+set semihosting enabled true
Semihosting server socket created at port 8000
+delete
All user breakpoints deleted
+tbreak spl_boot_device
Breakpoint 1 at S:0xFFFF1334
on file spl.c, line 71
on file spl.c, line 81
+run
Starting target with image E:\crl_ddr3_issue\cv_soc_devkit_ghrd_15.0\hps_workspace\Altera-SoCFPGA-HardwareLib-FPGA-CV-GNU\u-boot-spl.axf
Running from entry point
+wait
Execution stopped at breakpoint 1: S:0xFFFF1334
In spl.c
S:0xFFFF1334 71,0 {
Deleted temporary breakpoint: 1
+loadfile “$sdir/hwlib.axf” 0x0
Loaded section .ARM.exidx: S:0x0012078C ~ S:0x00120793 (size 0x8)
Loaded section .text: S:0x00100000 ~ S:0x00120717 (size 0x20718)
Loaded section .eh_frame: S:0x00120718 ~ S:0x0012078B (size 0x74)
Loaded section .ARM.exidx: S:0x0012078C ~ S:0x00120793 (size 0x8)
Loaded section .rodata: S:0x00120798 ~ S:0x00121027 (size 0x890)
Loaded section .data: S:0x00121028 ~ S:0x003565E7 (size 0x2355C0)
Entry point S:0x00100040
+start
Starting target with image E:\crl_ddr3_issue\cv_soc_devkit_ghrd_15.0\hps_workspace\Altera-SoCFPGA-HardwareLib-FPGA-CV-GNU\hwlib.axf
Running from entry point

Please suggest a solution for this issue.

Regards
Sudhendra

Hi @Sudhendra_Mishra:

I dont know how to solve your issue. But I have a question. What should I do to print the HWLIB in serial console so I can see the output in Putty?? It works when doing semihosting so I can debug from DS-5. I have done what the Readme says to print through serial console instead of DS-5 console: SEMIHOSTING=0 on makefile and comment int __auto_semihosting; in hwlib.c file. But it prints nothing through serial console
I have also lightly modified the Makefile to generate a .bin and put it on an SD to run. I have an SD with a preloader calling an u-boot in FAT32 and this confgures FPGA, enables bridges and loads and runs a .bin in the FAT32 partition. It works with othe baremetal examples so this is not the problem. When I run the .bin for HWLIB example from SD prints nothing either.

I would appreciate any help.

Thanks!

My Issue was resolved after modifying the Linker Script “cycloneV-dk-ram.ld” as below

/*ram (rwx) : ORIGIN = 0x100000, LENGTH = 1023M */
ram (rwx) : ORIGIN = 0x100000 + 0x40, LENGTH = 511M - 0x40

Regarding your issue, i haven’t seen such issue so far. As per my understanding Preloader checks for mkimage header. Make sure you have added it in your hwlib application image before writing into SD Card/QSPI Flash.

Regards
Sudhendra