This git repository might help you:
This indeed is implementing the steps given in FPGA Configuration, A-26 Cyclone5 handbook.
I tried to run the generated code on the DE10-nano. But unfortunately, after the step 4. ctrl.nconfigpull bit is set to 1, to pull down the nCONFIG pin of FPGA to enter reset phase. The linux reset is happening and reboot is trigerred after a few seconds. I am sure steps 1-3 are completed and also steps12-13 are met. Here are the register values:
MSEL Pin Configā¦ 0xa
FPGA Stateā¦ User Phase
cfgwdth Registerā¦ 0x1
cdratio Registerā¦ 0x3
axicfgen Registerā¦ 0x0
Nconfig pull regā¦ 0x0
CONF DONEā¦ 0x0
nSTATUSā¦ 0x0
ctrl.nceā¦ 0x0
Ctrl.enā¦ 0x1
dclk.dclkcntā¦ 0x5000
dclkstat.dcntdoneā¦ 0x0
Do point to what else is missing here!