Problem with fpga2hps Bridge

RocketBoards General
11

Hello,
I have found out the answer myself.
The proper way to reprogramme FPGA from running operating system is using DeviceTree overlays. The driver of Altera FPGA manager disnables and enables all necessary bridges itself and programmes FPGA with Raw Binary File (RBF) according to information written in DeviceTree overaly file (.dtbo).
I means that Yours Kernel have to be able to use DeviceTree overlays and support ConfigFS filesystem.
You can read more in Documentation in sources of Linux kernel code, especially here:
https://github.com/altera-opensource/linux-socfpga/tree/socfpga-4.9.78-ltsi/Documentation/devicetree,
https://github.com/altera-opensource/linux-socfpga/blob/socfpga-4.9.78-ltsi/Documentation/devicetree/bindings/fpga/fpga-region.txt.
DTS:

/*

  • This devicetree is generated by sopc2dts version 17.0 [9b3346002ac555f36b80b1bc56dad1cb86298234] on Thu Mar 01 11:38:46 CET 2018
  • Sopc2dts is written by Walter Goossens waltergoossens@home.nl
  • in cooperation with the nios2 community nios2-dev@lists.rocketboards.org
    */
    /dts-v1/;

/ {
model = “ALTR,soc_system”;
compatible = “ALTR,soc_system”;
#address-cells = <1>;
#size-cells = <1>;

aliases {
ethernet0 = “/sopc@0/ethernet@0xff702000”;
}; //end aliases

cpus {
#address-cells = <1>;
#size-cells = <0>;

  hps_0_arm_a9_0: cpu@0x0 {
  	device_type = "cpu";
  	compatible = "arm,cortex-a9-17.0", "arm,cortex-a9";
  	reg = <0x00000000>;
  	next-level-cache = <&hps_0_L2>;	/* appended from boardinfo */
  }; //end cpu@0x0 (hps_0_arm_a9_0)

  hps_0_arm_a9_1: cpu@0x1 {
  	device_type = "cpu";
  	compatible = "arm,cortex-a9-17.0", "arm,cortex-a9";
  	reg = <0x00000001>;
  	next-level-cache = <&hps_0_L2>;	/* appended from boardinfo */
  }; //end cpu@0x1 (hps_0_arm_a9_1)

}; //end cpus

…

sopc0: sopc@0 {
device_type = “soc”;
ranges;
#address-cells = <1>;
#size-cells = <1>;
compatible = “ALTR,avalon”, “simple-bus”;
bus-frequency = <0>;

…

  fpgabridge1: fpgabridge@1 {
  	compatible = "altr,socfpga-lwhps2fpga-bridge";	/* appended from boardinfo */
  	label = "lwhps2fpga";	/* appended from boardinfo */
  	clocks = <&l4_main_clk>;	/* appended from boardinfo */
  	reset-names = "lwhps2fpga";	/* appended from boardinfo */
  	resets = <&hps_0_rstmgr 97>;	/* appended from boardinfo */
  }; //end fpgabridge@1 (fpgabridge1)

  base_fpga_region {
  	compatible = "fpga-region";
  	#address-cells = <0x1>;
  	#size-cells = <0x1>;
  	fpga-mgr = <&hps_0_fpgamgr>;
  	fpga-bridges = <&fpgabridge1>;
  	ranges;
  };

}; //end sopc@0 (sopc0)

chosen {
bootargs = “console=ttyS0,115200”;
}; //end chosen
}; //end /

DTSO:

/dts-v1/;
/plugin/;
/ {
fragment@0 {
target-path = “/sopc@0/base_fpga_region”;
#address-cells = <0x1>;
#size-cells = <0x1>;
overlay {
firmware-name = “ArrowSocKit_AlternativeDesign.rbf”;
};
};
};

Application is described in documentation meant above, i.e
cat /lib/firmware/ArrowSoCKit.dtbo > /configs/device-tree/overlays/AlterantiveDesign/dtbo
while ArrowSocKit_AlternativeDesign.rbf is placed at /lib/firmware.

I hope this will help someone.