I was reading through this post /sys/class/fpga-bridge empty? and I have a slightly different issue… but maybe related? I am using a Cyclone V Dev Kit with Angstrom 2015.12 and kernel 4.1.33-ltsi. Also, I’m using the opencl.rbf instead of the standard soc_system.rbf shipped with the GSRD as I am working towards using opencl.
I can successfully insert the aclsoc_drv
But then I try to run a program, how about the vector_add example I am missing the required fpga_bridge files
Initializing OpenCL
Platform: Intel(R) FPGA SDK for OpenCL(TM)
Using 1 device(s)
c5soc : Cyclone V SoC Development Kit
Using AOCX: vector_add.aocx
Reprogramming device [0] with handle 1
sh: /sys/class/fpga-bridge/fpga2hps/enable: No such file or directory
sh: /sys/class/fpga-bridge/hps2fpga/enable: No such file or directory
sh: /sys/class/fpga-bridge/lwhps2fpga/enable: No such file or directory
Couldn't open FPGA status from /sys/class/fpga/fpga0/status!
sh: /sys/class/fpga-bridge/fpga2hps/enable: No such file or directory
sh: /sys/class/fpga-bridge/hps2fpga/enable: No such file or directory
sh: /sys/class/fpga-bridge/lwhps2fpga/enable: No such file or directory
mmd program_device: Board reprogram failed
MMD FATAL: acl_pcie.cpp:47: can't find handle -1 -- aborting
host_intel: acl_pcie.cpp:47: ACL_PCIE_DEVICE* get_pcie_device(int): Assertion `0' failed.
It looks like the bridges are registered properly on boot:
In my case the fpga_bridge folder is not empty and the bridges all have an appropriate entry for name:
root@cyclone5:~# ls /sys/class/fpga_bridge
br0 br1 br2 br3
root@cyclone5:~# ls /sys/class/fpga_bridge/br0
device name of_node power state subsystem uevent
Maybe these just need to be renamed? but I cannot just rename them live (not permitted), probably in a device table somewhere? Any ideas?
I am still thinking that these just need to be renamed appropriately (eg. fpga2hps) but I am not sure where to do that exactly as I cannot simply rename them while logged into the board,
Hello bmorcos,
I’ve hit the same problem trying to configure a DE10_standard board with kernel 4.7.0 and using OpenCL v17.
the names for the fpga bridge have gone from fpga-bridge to fpga_bridge and then named br0 -br3 under there.
Did you find a solution?
It would be useful if somewhere it stated which versions of kernels would run with the different version numbers of OpenCL. Has anyone seen a document that states this?
Unfortunately I haven’t found a solution and I haven’t looked much at this recently.
I got a little feedback from Intel saying that the new names (brx) are due to a driver rewrite, so my best guess would be a version mismatch somewhere in the BSP/kernel/driver/device tree or something. I really have no idea honestly.
I would be interested to hear if you make any progress. Have you tried compiling using the old kernel that is shipped with the design (I think 3.10 or 3.13 if I recall)? That was next on my list before I put it on the back burner.
Hello,
could I ask You about any progress in problem of enabling/disabling bridges? I have been searching for the answer and trying myself various manners practically for quite a long time but I am still not able to controll state of bridges. It seems not to be any official information about the change of behaviour of bridges.
I am using Linux kernel 4.1.22-ltsi (even if the version 4.1.33-ltsi should be supported by Intel/Altera now).
I thanks for any answer in advance.
Best wishes, Jan Konecny.
Application is described in documentation meant above, i.e cat /lib/firmware/ArrowSoCKit.dtbo > /configs/device-tree/overlays/AlterantiveDesign/dtbo
while ArrowSocKit_AlternativeDesign.rbf is placed at /lib/firmware.
@JanKonecny Thank you - your information is quite relevant and helpful. It is still a “learning experience”:
Few sleepless nights passed and now I am getting results: “Kernel Panic” Negative result is also a result, right? I may highly benefit form additional pointers since things might have evolved over the time with new kernels(?)
DE0-NANO-SoC
4.14.130-ltsi-socfpga-r2 (Debian 10 - if that is relevant)
> root@arm:/lib/firmware# dtc -O dtb -o fpga_config.dtbo -b 0 -@ fpga_config.dts
> fpga_config.dtbo: Warning (avoid_unnecessary_addr_size): /fragment@0: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
mkdir /sys/kernel/config/device-tree/overlays/fpga_config
echo fpga_config.dtbo > /sys/kernel/config/device-tree/overlays/fpga_config/path
[13009.641348] OF: overlay: find target, node: /fragment@0, path '/soc/base_fpga_region' not found
[13009.650092] OF: overlay: init_overlay_changeset() failed, ret = -22
[13009.656344] create_overlay: Failed to create overlay (err=-22)
If anyone is willing to share more recent information and preferably tested overlay file I would appreciate it tremendously. I may even get back to what I wanted to do two weeks ago - start FPGA coding )
I managed to create my own rbf file and make it configure the FPGA portion of the SoC from uboot. My ultimate goal is to read/write fet of FPGA registers from Python. Pointers to any working solutions may allow me to get more sleep than I am getting right now.
(And if Honza doesn’t mind direct messaging - we speak the same language).
Best regards form California and thanks for reading that far.
Martin