Hello,
I’m trying to boot the hps with the default achilles-console-image-achilles.wic after modifying the .itb files on the emmc but i have the following error after rebooting :
U-Boot SPL 2021.07 (Dec 02 2021 - 03:12:39 +0000)
Error: Could Not Calibrate SDRAM
DDRCAL: Failed
FPGA: Checking FPGA configuration setting …
FPGA: Skipping configuration …
WDT: Started with servicing (10s timeout)
Trying to boot from MMC1
The only step i have done beside the writing of the .wic
dd if=achilles-console-image-achilles.wic of=/dev/mmcblk0 && sync
is generating the itb with the .rbf files generated by quartus/quartus_cpf using the documentation found here
ln -s <path/to/rbf/files>/achilles_ghrd.periph.rbf
ln -s <path/to/rbf/files>/achilles_ghrd.core.rbf
tools/mkimage -E -f board/reflexces/achilles/fit_spl_fpga_periph_only.its fit_spl_fpga_periph_only.itb
tools/mkimage -E -f board/reflexces/achilles/fit_spl_fpga.its fit_spl_fpga.itb
and copying it on the right partition of the emmc
mkdir -p /media/emmcp1; mount -t vfat /dev/mmcblk0p1 /media/emmcp1; cd /media/emmcp1
scp <…>*.itb .
poweroff
Then turn off the board and turn on the board and then i have the error message.
I have tried with a rebuilt (with the hps.xml → socfpga_arria10_achilles_handoff.h) uboot.img and uboot-spl without any changes.
Hardware side, we work with Quartus 17.0 and use the “Arria 10 Hard Processor System” and “Arria 10 External Memory Interface for HPS” (EMIF) from IP Catalog of Quartus and link them with Qsys.
The HPS use lightweight HPS-to-FPGA interface with a 100 MHz clock from a PLL and the EMIF is a DDR4 and configure in Early I/O Release mode.
For the reference clock of the EMIF, it is linked on the AL27 pin for FPGA and try to configure with ClockBuilder Pro at 300 MHz.
So, do you have any idea why we are getting the SDRAM/DDR CAL error ??
Do we miss something important ??
Thanks a lot for your help !
Fabien