Adding .svd file to debug configuration leads to fail in DS-5

Hi all

I’m currently new to the whole FPGA SoC Topic and I was working trough a lot of the tutorials provided by rocketboard. For the following up project I’m using the Cyclone V SoC Development Board. I’m not using any OS on top of the HPS (bare metal applications). The Qsys Configurations are pretty similar to the GRHD I was barely skipping some of the peripheral pins (since we won’t have them on our own PCB in future projects) and the soc system designed with Qsys is not the top level entity but an instance in an .bdf file. The pin / location assignment has been done in a similar way as the grhd_top has been done (provided by the SoC EDS).
I’m currently facing some problems using the DS-5 Debugger when I add the .svd file to the debug configuration.
The FPGA has been configured by u-boot and the preloader has been running successfully (to set up SDRAM, etc.). I also enabled the bridges by the “run bridge_enable_handoff” command.
So far I’m not able to start the application when the .svd file has been added. Furthermore if I do not add this file the application starts but then refuses to write e.g. the LED registers (the qsys_header files have been generated and added correctly, s.t. the address macros should be correct).

The following messages are prompted to the command line:

Connected to running target Altera - Cyclone V SoC (Dual Core) on TCP:localhost
Stopping running target Altera - Cyclone V SoC (Dual Core) on TCP:localhost on connection
Execution stopped in SVC mode at S:0x3FF90D9E
S:0x3FF90D9E BX lr
cd "C:\SoCWorkspace\src\software"
Working directory "C:\SoCWorkspace\src\software"
Execution stopped in SVC mode at S:0x3FF90D9E
S:0x3FF90D9E BX lr
source /v “C:\intelFPGA\16.1\embedded\ds-5\sw\debugger\configdb\Scripts\altera_target_check.py”
+print &$Peripherals::$rstmgr::$rstmgr_brgmodrst
$1 = (unsigned int*) P:0xFFD0501C
Checking SYS ID registers
Checking Peripherals::altera_avalon_sysid_sysid_qsys_0_control_slave::altera_avalon_sysid_sysid_qsys_0_control_slave_ID
+print &$Peripherals::$altera_avalon_sysid_sysid_qsys_0_control_slave::$altera_avalon_sysid_sysid_qsys_0_control_slave_ID
$2 = (unsigned int*) P:0xFF200170
ERROR(?): DebugException: Failed to read 4 bytes from address AHB:0xFF200170
File “C:\intelFPGA\16.1\embedded\ds-5\sw\debugger\configdb\Scripts\altera_target_check.py”, line 137, in
displayAndCheckSysIdReg(execContext, regs, regName)
File “C:\intelFPGA\16.1\embedded\ds-5\sw\debugger\configdb\Scripts\altera_target_check.py”, line 86, in displayAndCheckSysIdReg
val = getSysRegValue(execContext, sysReg)
File “C:\intelFPGA\16.1\embedded\ds-5\sw\debugger\configdb\Scripts\altera_target_check.py”, line 103, in getSysRegValue
val = getAddrValue(execContext, addr)
File “C:\intelFPGA\16.1\embedded\ds-5\sw\debugger\configdb\Scripts\altera_target_check.py”, line 11, in getAddrValue
val = context.getMemoryService().readMemory32(addr)
File “pyclasspath/arm_ds/internal.py”, line 13, in wrapException
ERROR(CMD656): The script C:\intelFPGA\16.1\embedded\ds-5\sw\debugger\configdb\Scripts\altera_target_check.py failed to complete due to an error during execution of the script
loadfile "<C:\SoCWorkspace\src\software\baseprojectSw_v1\Debug\baseprojectSw_v1.axf"
ERROR(CMD16-TAD274-NAL52):
! Failed to load “baseprojectSw_v1.axf”
! Failed to write 80’144 bytes to address S:0x00100000 while writing block of 4’096 bytes to address S:0x00100000
! Cannot attain state requested.
set debug-from main
start
WARNING(CMD399-COR168):
! Failed to start the target
! No function named “main” could be found
WARNING(CMD407): Trying the entry point instead
ERROR(CMD426): Cannot find symbol to start or entrypoint, the file or load commands may be used to set the entrypoint
wait
break -p *S:0x001118F4
Unable to set software breakpoint, falling back to hardware breakpoint
ERROR(CMD27-TAD12-NAL52):
! Failed to set a breakpoint
! Unable to create breakpoint at S:0x001118F4
! Cannot attain state requested.
Target Message: Could not determine target state
Target Message: Could not determine target state
Target Message: Could not determine target state
quit
Disconnected from stopped target Altera - Cyclone V SoC (Dual Core) on TCP:localhost

Additional: To verify that the boot process has been finished successfully:

U-Boot SPL 2013.01.01 (May 23 2017 - 13:26:53)
BOARD : Altera SOCFPGA Cyclone V Board
CLOCK: EOSC1 clock 25000 KHz
CLOCK: EOSC2 clock 25000 KHz
CLOCK: F2S_SDR_REF clock 0 KHz
CLOCK: F2S_PER_REF clock 0 KHz
CLOCK: MPU clock 800 MHz
CLOCK: DDR clock 400 MHz
CLOCK: UART clock 100000 KHz
CLOCK: MMC clock 50000 KHz
CLOCK: QSPI clock 400000 KHz
RESET: COLD
SDRAM: Initializing MMR registers
SDRAM: Calibrating PHY
SEQ.C: Preparing to start memory calibration
SEQ.C: CALIBRATION PASSED
SDRAM: 1024 MiB
SDRAM: Initializing SDRAM ECC
SDRAM: ECC initialized successfully with 1563 ms
SDRAM: ECC Enabled
FPGA : Programming FPGA
ALTERA DWMMC: 0
reading soc_system.rbf
reading soc_system.rbf
FPGA : Programming FPGA passed

U-Boot 2013.01.01 (May 23 2017 - 13:26:53)

CPU : Altera SOCFPGA Platform
BOARD : Altera SOCFPGA Cyclone V Board
I2C: ready
DRAM: 1 GiB
MMC: ALTERA DWMMC: 0
In: serial
Out: serial
Err: serial
Net: mii0
Hit any key to stop autoboot: 0
SOCFPGA_CYCLONE5 # run bridge_enable_handoff
Starting application at 0x3FF795A4 …
Application terminated, rc = 0x0

I already spent hours to track down this errors but I’m actually a little bit lost. Any help would be gladly appreciated.

Best

Stefan

Hopefully, this link helps you.

https://rocketboards.org/foswiki/Projects/UsingCMSISWithCustomFPGALogic