Hello,
I’m using the DK-DEV-AGI027RBES devkit. GSRD provided images at Rocketboard boots-up with yocto Linux. I have re-generated sof file for gsrd using quartus prime prom 24.1 (by removing NIOS-V core) and followed the steps at Rocketboard wiki to re-compile yocto to generate images.
I tried loading - cmc_hps_fm85_hps_auto.sof (merged with bootloader), u-boot interrupts the process with the following error:
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Can anyone help me if I’m missing something or am doing something incorrectly?
Looking at the log, it appears that SPL booted normally.
After that, SPL appears to be unable to load u-boot.
The GSRD url you referenced has the following content.
I think it would be a good idea to check this part again.
Note: If package command fails and unable to locate u-boot.itb and u-boot-spt-dtb.hex please look inside the following path respectively
Thanks for your comment, the package command completed without any error messages and I see the images under the “agilex_fm61-gsrd-images” folder. Anyway I re-check.
I see in *.map file below, hope that’s the expected, please comment if any!
GSRD provides only SD boot mode prebuilt images.
It would be a good idea to recheck whether the boot mode is set properly.
I also had a similar issue. In my case, hardware design files(*rbf, *its) were invalid.
I hope the issues I experienced will help you solve your problem.
Thanks.
Development kit DK-DEV-AGI027RBES does NOT have an SD card slot, the GRD provided in the rocketboard wiki says agilex hps boot from QSPI flash connected to the MAX10 FPGA - HPS Example Design for Agilex 7 I-Series DevKit (2x R-Tile and 1x F-Tile) | Documentation | RocketBoards.org
I flashed the pre-built images from the wiki and was able to get the kit to work with Yocto Linux. The switch settings strapped in the same position rest of its life. The new attempt was that I rebuilt yocto from gitcheckout following the steps provided in the wiki, and then used the quartus_pfg tool to merge the new fsbl image (tried to configure it via Jtag), and the resulting *_hps.sof file was the one I loaded via the Quartus programming tool. I’m expecting this program put the spl into the arm boot ram, let arm boot. spl direct arm to boot further qspi to extract the rest of the images (u-boot, kernel) available in qspi flash (which is the flashed gsrd image).
When I power cycle the kit boots fine and when the program sof added spl images the boot flow drops with message cannot find the spi flash - [in the tera-teram image]
The twist with this kit is agilex qspi attached to max10. after power on the sdm comes up in the agilex and look for images through AVST path, this parallel bus is connected with Max10. the max10 cpld image provide access to QSPI to agilex sdm.
I recently switched from Xilinx to Intel Altera looking for advantages in the HPS world, i’ve limited knowledge here, lot to know, but Can you describe the *.rbf files, Can Agilex devices also be programmed using this instead of *_hps.sof? fpga fabric + sdm helper image
Actually, I only do work related with HPS.
My colleague is in charge of the things related with FPGA Logic or hardware design.
I have developed mostly ARM based Linux system. So I have no idea about hardware design.
I use Arria10 SDK now. Although the SDK is not same, there are binaries related to SPL, u-boot, spl_fpga*.itb.
In my case, SPL, u-boot image was no problem, but fit_spl_fpga.itb(fpga releated) was invalid.
And… As you may already know, you need to build using defconfig for QSPI before building u-boot. like below
If you use QSPI instead of sd bootmode, it may be work.
cd $WORKDIR
git clone -b langdale https://github.com/altera-opensource/gsrd_socfpga
cd gsrd_socfpga
#. agilex_fm61-gsrd-build.sh //script for sd boot mode
. agilex_fm61-qspi-build.sh
build_setup
This url is a document related to how to build a simple image consisting of only u-boot, kernel, and rootfs, so it might be a good idea to refer to it.
I’m also planning to switch to Agilex soon few month later, but I don’t know much about Agilex FPGAs. So there is no advice I can give. I hope you solve the problem.
Hi sy13,
No problem, thanks for your comment, very appriciate. I’ve found that most Intel kits have similar requirements for images and processes of generation, Changes may be made at the device tree level to map boot devices correctly for the engine to work properly. I’m missing something very basic in the end, I come from an fpga hardware background but trying to quickly recreate gsrd before I take my new design and deliver it to software folks, HPS altera is new to us and trying to digest the flow and enable!
the flow i’m using bitbake to build the yocto and i see the rootfs folders have sources which similar to the buildroot, let me explore other ways!
Hi,
I have generated a sof with “generate programming file” setting - hps first and see that spl is able to get the gsrd image in the qspi flash, the spl file i’ve generated freshly following the rocketboard wiki.
FPGA IO seems to preventing ARM while fetching images(u-boot/kernel) from QSPI via active serial mode when FPGA first configuration mode enabled, Any thoughts on here?
Do we need to mention the image partitions of aspi in the DTS of kernel/u-boot? Below is what I see when feeding the *.pfg file to quartus_sh, the same address is mentioned in pfg. How does the processor know these addresses and where does it need to be mentioned when compiling u-boot/kernel?
