Altera Cyclone V SoC Dev Kit and SignalTap II Issue

1

I am working with the Altera Cyclone V SoC development kit and I’m having an issue with the SignalTap II logic analyzer.

I was initially able to add the block to a simple Quatrus project and debug different signals in the project. However after some changes I am receiving the following errors when I download a .sof file through the SignalTap II window.

Info (209016): Configuring device index 2
Info (209017): Device 2 contains JTAG ID code 0x02D020DD
Error (209040): Can’t access JTAG chain
Error (209015): Can’t configure device. Expected JTAG ID code 0x02D020DD for device 2, but found JTAG ID code 0x00000000.
Error (209012): Operation failed

The device is programmed, I can tell by a change to the LED configuration on the board, but once I get these errors the SignalTap II window indicates “Invalid JTAG configuration” highlighted in yellow next to the Instance Manager and there is no way to run the analyzer.

I have removed the changes, but the issue persists. One thing that concerned me is that when the analyzer comes up there are 3 options to program the .sof file to, with option 2 being the correct choice to program the FPGA but option 1 being selected by default:

@1: SOCVHPS (0x4BA00477)
@2: 5CSEBA6(.|… (0x02D020DD)
@3: 5M2210Z/E… (0x020A40DD)

I noticed this issue after I mistakenly attempted to upload the .sof file to @1. Has anyone here seen a similar issue with SIgnalTap II and have a solution?

2

HI!!
Its important to know that if you changed something in your design or SignalTap, you have to Recompile the whole project.
Then try to program the FPGA using tools>programmer in Quartus! If it works just open SignalTap and setup the jtag cable. SignalTap will be ready to use!
If it doenst work, you probably have a problem with the Jtag cable or driver!
And …yess @2: 5cseba6 is OK… thats the FPGA.
@1 is the HPS, and @3 is the MAX5 on the board. They are all in the same daisy chain (JTAG).
hope it helps!
bye
M

3

Thanks for the reply. I’m finding that this issue is linked to the Sample Depth used in SignalTap and the Altera dev kit with built in USB Blaster.

When I get to larger sample depths (32k or so), the design compiles just fine, and looks to download just fine, but SIgnalTap gives me a bunch of errors when I try to run it, when I step back to 8k or so sample size it seams to work just fine, this is on the Altera dev kit with the built in USB Blaster 2.

I also have another Cyclone V SoC module with out the USB Blaster built in, using an external USB Blaster connected to this board lets me use any sample depth and it looks like it’s working fine.