Altera SoC Triple Speed Ethernet Design Example

Hi there

I got a Cyclone V SoCDevelopment Kit and I would like to run the TSE example here on rocketboards. I need the two Ethernet ports for an upcoming projects where I want to have a daisy-chain configuration. My idea was to start with the example, as this should be straight forward… it’s sadly nod so easy:

  • I was able to build the FPGA design (depending on the Quartus version, I needed to reduce the size of the SignalTap IP. The IP in the project files is too big)
  • I was able to create the Yocto with the with the altera_tse driver.
  • The system boots and loads the driver.

But I only can receive packets on these 2 drivers. When I make ping/or arping, the device sends nothing, it also doesn’t trigger the sgDMAs for TX. However, if i ping the devkit from my laptop, the correct MAC address gets written into the ARP-table of my Yocto.

Does anybody have a working SW-FW design or any good advice for me? I’m here in the past 3 weeks. My next seps are now to add some printf in the altera_tse driver and try to find out what’s going wrong with signalTap.


Link to project: