Arria 10 Boot error!

i’m using an arria 10 SoC , and i’m configuring the FPGA via the HPS using rbf file, when booting the system this error occurred.

U-Boot 2014.10 (Apr 27 2017 - 09:51:27)

CPU : Altera SOCFPGA Arria 10 Platform
BOARD : Altera SOCFPGA Arria 10 Dev Kit
I2C: ready
DRAM: WARNING: Caches not enabled
FPGA: writing socfpga.rbf …
FPGA: Poll CD failed with error code -10
INFO : Skip relocation as SDRAM is non secure memory
Reserving 2048 Bytes for IRQ stack at: ffe386e8
data abort
pc : [] lr : []
sp : ffe3def8 ip : 0000001c fp : 00000001
r10: ffd02078 r9 : ffe3ff38 r8 : ffe00054
r7 : ffe2043c r6 : ffe203e8 r5 : 00000000 r4 : ffffd000
r3 : ffcfb000 r2 : 00000002 r1 : 00000004 r0 : 00000001
Flags: nzcv IRQs off FIQs off Mode SVC_32
Resetting CPU …

resetting …

Dose anyone know the reason of this error ? can i fix it ?
thank you

Just thinking out loud:

  1. Did you boot the bsp-editor, select your handoff folder and create the u-boot framework or use some other preloader binary?
  2. Did you specify an rbf filename of “socfpga.rbf” when you used the bsp-editor and place that rbf on your fat partition?
  3. Do you have a single rbf or a “core” and “periph” early IO release rbf set?
  4. are your rbf files in the proper format?
  • sof to rbf for a single rbf: (using the soceds terminal)
    quartus_cpf -c -o bitstream_compression=on myfilename.sof myfilename.rbf
  • sof to rbf for early io release core and periph rbfs:
    quartus_cpf -c --hps -o bitstream_compression=off myfilename.sof myfilename.rbf

If using a core and periph rbf set you should specify the periph rbf filename in the bsp-editor.

Hope something here helps.


Thank you for your response sir, i think the problem was in the rbf file format, i needed to make sure that the sof is will converted and the rbf is fully copied to SD card.
the error is gone,