for an academic project, i’m using Arria 10 SoC , first i wanted to learn how to use the board,
I started by ruining linux on the arm side (which i did), now i want to manipulate the FPGA side of the board by a blinking led project using Quartus Prime, i wrote the VHDL script , and now i’m stuck , i don’t know what to do exactly to load the project into the board.
also the project is about communication between the ARM and FPGA (HPS/FPGA) Arria 10 , any advices on how to begin , what to learn for a beginner.
In DE1-SoC CD there is an example on how to blik a led. They put a GPIO in the FPGA and connect it to the processor using the Lightweight HPS-FPGA bridge. In Qsys they assign address X to the component. This is relative to the bridge. Then they export from Qsys the signals to outside Qsys, compile Qsys. Connect the exported LEDs of the Qsys signal to the LEDs pins. Compile Quartus and use the programmer to load it. Then in the processor you have to create a C program that access address_of_lightweight bridge + X to access the GPIO. TO do so you can use mmap to obtain virtual address of the hardware address of the GPIO. You should have a similar project in your board documentation or you can follow the DE1-SoC one.
In case you only wanna blink the led using FPGA only you just load the design in the FPGA. FPGA and processor work independently of each other so you can work with FPGA as an independent FPGA. Asign pins for the input clock and output LEDs. Compile. Use programmer to load the design using the blaster II to USB port. There should be tutorials for your board or other boards. Check DE1-SoC board tutorials. There are only HPS, only FPGA and HPS-FPGA example projects.
Thank you for the response , this is very helpful.
I successfully loaded a project into the FPGA using USB blaster II, but this project dosn’t contain any leds (as output) or switches (as INPUT), what i need to do now is to test the project (it’s loaded on the board),
for example , i have 64 inputs and 64 output ,
to obtain the output i want to enter input value and each time i need to verify the output values and frequency
to be sure that this project works… is it possible to do it with Quartus or is there any other method ?
Well, you can do simulation using Model-Sim Altera (freely installed with Quartus) to test is some VHDL works. I use Nativelink flow. You should be able to find a tutorial overthere. Nativelink makes ModelSim Altera open and run time simulation automatically doing a click from Quartus.
Then using the board you have to assign pins to the inputs and outputs of your design. Lets say you do a AND gate with 2 inputs. You can connect the 2 inputs to Switch 0 and Switch 1 and output to a LED. All boards have a manual where you can see which pin of the FPGA is using each resource in the board (led, swich, pin headers, etc.) To do that you can use assignments->pin planer in Quartus or manually add them to the .qsf file of your project. In the board documentation there is usually examples assigning all the pins of the board so you can just copy all the pin assignments from the example .qsf to your .qsf file.
Thank you for your answers, but i feel like i didn’t explain well , let me rephrase ,i have done functional and temporal simulation using Model-Sim and Time quest analyzer (freely installed with Quartus) . after running time simulation i get that my design will be operating at a frequency of 500Mhz , what I’m afraid of is that there could be some material issue (may or may not occur) that could lower the frequency value for example … so i need to verify with an inboard test (maybe),
my question is:
is it possible to verify ? if so how ? is there any debugging tool for FPGA?
again Thank you,
Time quest analyzer tells you the maximum frequency you can run the design but the clock is supported by an external oscillator, tipically 50MHz, and your design will run at that speed. You can speed up that using a PLL from 50 to 500 and test if it works.
To test the FPGA you the Signal Tap Logic Analyzer that is a logic analyzer that you can build inside the FPGA to sniff the values of your signals. It is in Quartus -> Tools -> Signal Tap Logic Analyzer. You add signals you want to see on the left and the system clock in the right. You select a trigger signal to produce a capture and and recompile again.
However Quartus Timeques analyzer is very conservative, like 30% and if quartus tells you it can run at 500 thats the true and the best way to define the maximum frequency you can run the design. Logic lock analyzer is dangerous because it may run well now but you maybe close to the point of failure appears and maybe later when the room is hotter the design fails. The best way to know the max frequency is what you did. And then test if it works in real life. I use logic analyzer to debug processor-fpga connection only.
OK the vision is clear , thank you sir for your effective advices .