Arria V HPS GMII to SGMII through FPGA

We’re trying to use the CycloneV SGMII Example Design from the Rocketboards projects to give us a 1000BASE-KX Ethernet connection using EMAC0 in the HPS through the Altera GMII to SGMII Converter, but we’re implementing it on an Arria V SoC instead of a Cyclone V. We are using a Linux version that we have used on numerous other Arria V projects, the Altera SoCFPGA Linux from Altera’s OpenSource GIT Hub branch 4.2 (SoCFPGA-4.2). So far we have only been able to get the Ethernet connection up and running with a couple of workaround steps. At power up we have to halt the bootloader (U-boot) before it loads the kernel. We then have to reload the FPGA fabric with our SOF even though we are using an EPCQ to program the FPGA side at power up. Then we boot the Linux kernel, which will bring up the eth0 connection but we get a NETDEV Watchdog timeout (NETDEV WATCHDOG: eth0 (socfpga-dwmac): transmit queue 0 timed out) a couple seconds later. We can usually bring the eth0 connection down, and then back up again, and then we will have an Ethernet connection. It’s a messy workaround that we cannot support in the final design.

Has anyone been able to get the HPS to SGMII Ethernet Linux + FPGA Converter code working? Anyone get it working on an Arria V? What version of Linux did you use? Does anyone understand why we would need to stop the bootloader from loading loading the kernel, then reprogram the FPGA fabric before booting to Linux? It must be some sequence timing thing, but we’re not sure what it could be. We have been successfully using this board for other things for about a year now so we know that the EPCQ configuration is working on the board.

I forgot to mention that I did have to slightly modify the GMII to SGMII source code to clear the Control bit in the Altera GMII to SGMII Adapter core to allow transmission out of the FPGA. The Control bit in the file altera_gts_csr.v file is a tx_disable, and was being reset to a value of ‘1’. We couldn’t find anywhere in the driver code that would clear this bit to allow transmissions.

Any suggestions or insight into these problems would be greatly appreciated. Thanks!