Hi everyone. I need help to boot my custom SoC using the Arria10 as the FPGA.
The DDR controller fails on calibration error during U-Boot execution. It fails because of the PPL used as its reference clock.
Indeed, this PLL is driven by a physical device external to the Arria10. This device is mastered by an FSM in the programmable logic part of the FPGA.
The problem is that the DDR controller starts the calibration while the PLL is still in its initialization phase, thus creating a race condition. I think a solution could be completely resetting the DDR controller once the PLL initialization is complete. However, I can’t find a way to do this in U-Boot.
Do you know a way of completely resetting the DDR controller without resetting the HPS (like Quartus Programmer does)? A bit to set or a signal to trigger?
Thanks in advance for your answer.