Avalon-MM waitrequest stuck (Cyclone 5 F2SDRAM)

Hi, I’m having trouble trying to access HPS memory from the FPGA in a Cyclone 5.
I have configured an Avalon-MM Interface to be a master to the F2H_SDRAM read-only-interface in Qsys.

Now, when I set the read signal of the Avalon bridge to high, the slave asserts the waitrequest signal, but never deasserts it, so the transaction is stuck. (dcb_write is just my internal signal to start the transaction)

Any idea what could cause this? I’m still fairly new to this, so I’m kind of hoping for it to be some obvious misconfiguration.

Edit: One idea I had was that I might need to configure the SDRAM controller subsystem through its CSR, but I couldn’t find anything on how to actually do that.

Update: it got worse somehow. Now waitrequest ist being asserted all of the time from the beginning, without me interacting with it. Any help would be greatly appreciated.