Bare metal memory map

I’m working on getting at the basic memory map of the system at a bare metal level. I’m having a hard time finding information outside of using linux with u-boot. Can anybody point me to information on how the memory map is layed out with the memory manager disabled? Right now I’m loading u-boot to get the system functional then loading programs through eclipse. It looks like the SDRAM starts a 0x0 but my FPGA design maps a peripheral to 0x0 also. I can access the memory mapped registers in the HPS from the datasheet but I’m missing how the DDR maps into the memory space along with any peripherals I’ve added when I build the FPGA. Initially I would like to disable the MMU and use the address space linearly, but its difficult to figure out because invalid accesses break the emulator environment.

First, how do I disable the MMU to have access to the complete memory space without causing a fault and second, when I create a peripheral how do I map it to a useable location in memory?

All help is appreciated.

The memory map for Cyclone V SoC comes in its handbook, in the end of 1st chapter in vol.3.
The HPS-FPGA bridge starts at 0xC0000000 for the processor. And the lightweight at a higher position. All this mapping is solved by L3 by hardware and its the same for baremetal and os. Once you enter the FPGA through the bridge you have to create the submapings with qsys. In qsys you asign address relative to the avalon or axi master. Therefore if you connect a peripheral in fpga to HPS-FPGA bridge and in qsys its address is 0x000000A0, the address of the peripheral as seen by the processor is 0xC0000000+0x000000A0=0xC00000A0.
Regarding the MMU i am almost sure that MMU starts switched off in baremetal. Maybe your uboot switches it on. Anyway, in i have 2 examples you can use. They start with mmu off. I am sure of that because there is big increase in performance when i switch it of using the cache functions

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