Bizarre Verilog FSM error, please help explain

I am designing a Manchester receiver. The design simulates in modelsim. I synthesized the code and downloaded it to a de10 nano cyclone V fpga to test it, and I used Intel/Altera’s signal tap logic analyzer tool to analyze the signals. I observed this strange error occur once. I’m really confused and curious. My state machine transitions from state 4 to 13, but state 4 can only transition to states 15, 9, or 5. How is this possible? I have posted the code for state 4 below, and a screenshot of the logic analyzer result.


Hi Nick,
Which states transition to 13 according your design?
Maybe the error is not in state 4?

Otherwise, might it be a glitch in the clock signal?


Does your design have timing closure? I’ve found when I clock state machines a bit faster than they should this sort of unexpected result can occur. State 4 is a bit busy (mostly driven by the levels of nesting in its logic) so if it cannot complete its actions before the next rising edge of the clock driving it then the bits that compose the register ‘state’ will be set incorrectly (sometimes partially set in one state - then in another so it results in an impossible state!).
Running Timequest to get closure would help tell if this is the case. Also just slowing the clock to the state machine could help in diagnosis to see if the error stops. If the error occurs rarely that may not help much, but I would suspect a timing issue.

I think it was a metastability issue. The signal “transmitted_data” was not synchronized to the clock domain of the state machine.