So you want to configure the FPGA and have u-boot run from fabric memory?
If that’s the case then the 20.3 flow is what we use. You obviously need to set the Quartus platform designer project up so that it boots the HPS from the FPGA. There are a couple of places this needs to be set, in the HPS properties within Platform Designer select “Enable boot selection from FPGA” then select the FPGA as the boot source. You also need to disable the “Enables the HPS early release of HPS IO” from the “Device and Pin Options” under the main “Assignments->Device” menu.
In addition you need to create one or two embedded block RAMs which will hold the u-boot SPL and main images, these will map into the HPS address space in 0xcxxxxxxx, I think we have SPL at 0xc0000000 and main at 0xc0080000.
For u-boot just clone the Intel u-boot repo, we use 2020.04. You need to get the hps_isw_handoff folder from the firmware project and pass that through the bsp-create-settings embedded tools script to generate the u-boot handoff dtsi file. That needs to go into the u-boot arch/arm/dts folder, you may need to include/replace an existing handoff file or create your own boards top level dts file to include the handoff file, this depends on the u-boot version as they have reorganised that recently. Then just build it.
Once built you can convert the SPL and main binaries to Intel hex format and provide those to the firmware project to initialise the block RAMs created there.
That’s it, should just work now.