Compile error Hardware design for Atlas SoC on QP 16.1

Linux Kernel
1

Hi,

I’m a newbe on de0-nano-soc.

I would like to be able to compile the hardware design for de0-nano-soc, the idea is later to make a driver to the FPGA fabric.

I went to rocketboards.org > Atlas SoC > Compiling hardware design and preloader

I use the SoCEDSSetup-16.1.0.196-windows toolchain, I have windows 10 (x64).

It goes very well, at least until line 5569 of the log file, where it reaches a “time limited” file.

/atlas/atlas-soc-ghrd/ATLAS_SOC_GHRD/output_files/ATLAS_SOC_GHRD_time_limited.sof contains time-limited megafunction that supports OpenCore Plus feature -- Vendor: 0x6AF7, Product: 0x0034
Warning (11713): The configuration of the Hard Processor Subsystem (HPS) within this design has changed.
The Preloader software that initializes the HPS requires an update.
Using hps_isw_handoff/soc_system_hps_0/, run the Preloader Support Package Generator to update your Preloader software
Error: Quartus Prime Assembler was unsuccessful. 1 error, 4 warnings

Does it means that the open source stuff contains items that can be compiled only with paid (and not very cheap) QP ?

Any idea welcome :wink:

2

That is a bit weird for a GHRD, there’s no such thing for the Arria10 for instance. Maybe there are several versions of this design? At worse you could try regenerating this SOF yourself, removing any time-limited part of the design (as long as it’s not critical…).

But yeah the “time limited” thing means that it’s an evaluation design that can’t be run for a long time untethered. When I use these time-limited sofs during development I load them directly through the JTAG using quartus_pgmw. Then as long as I keep the JTAG connected and quartus_pgmw running the FPGA will work normally. If I disconnect the JTAG it’ll eventually stop working (not sure how long it lasts, I believe it’s design-specific). This way you can test an expensive IP module without having to buy it first.

I don’t know if you can boot up a time-limited SOF normally (i.e. by flashing it instead of loading it through JTAG), but I think the timeout would make it a pain to work with anyway.

3

Hi Lionel,
Thanks for the answer
Ok, will investigate this in detail and let you know here. Hope to get the root cause at some point.

4

I had the same problem but, unfortunately, I had so many show-stoppers before I got a clean compile, I cannot remember exactly how this one was fixed! (I don’t keep good enough notes.)

I think you have to toss the offending IP and I suspect it was the FFT demo module built into the Atlas GHRD.

BTW. The Atlas GHRD pre-requisites name Quartus 15.0, but it won’t compile on the free version of 15.0! Before building with 16.1, you might want to run Quartus or Qsys to update all the IP to 16.1.

BTW2: You only need to rebuild Pre-loader and U-boot if you change the boot source to other than SD-Card.

BTW3: The Quartus-built Device Tree does not have a working Ethernet. I hand modified the one on the supplied SD-card!