Hello,
i am trying to compile the “PCIe Root Port with MSI” with one of the new quartus versions. But it fails dramatically, in the terms of timing. I just get about 90 MHz(coreclk), but need 125 MHz. There are a lot of messages about ignored timing constraints but they also appear in the version 13.1 to. But anyhow they are generated by the toolchain or come with the example. So they should work. I tried to fix them by hand, but the result is still much to slow.
On the page of the example is written: "Status: Quartus II 14.0"
So somebody should have already compiled the example successfully.
Is there a away to fix this by writing completely new constraints? Or is there a other trick?
I am also trying to compile the reference design myself but with 15.0 tools. Have you tried to run the design with that firmware build, and if so, what outcome are you seeing?
This might be related the problems that I am seeing, not sure about the timing problems you saw however:
https://www.altera.com/support/support-resources/knowledge-base/solutions/rd07312015_568.html
I have tried version 15.0. It failed. Then i tried 14.0 because it was mentioned in the tutorial. I have redone some of the constraints, not the false paths, and increased the limit of the interconnect pipeline stages to 1. The default value is 0. Due to lack of time, i only compiled it. Now it looks better on chip planner. Before this, the design was scattered along the fpga. I now get 136 MHz max.
It looks like the newer version cannot understand the clock constraints from the older version.
I think If all the clock constraints would be done right, it would probably produce the same result as the old version.
Hey,
Does any body have a design overview of this design. I am trying to understand the address maps of the system and how different components are connected. Please let me know!!!