Configuring FPGA hangs Linux on DE10-Nano

I’m using the stock DE10-Nano SD-card and its U-boot/Linux config. When I configure the FPGA over USB Blaster with DE10_NANO_SoC_GHRD that came with the system CD, it works great. I’m able to hit the lightweight AXI bridge from Linux, set the LEDs, and check the status of the switches. I can also re-generate Qsys-generated files and it still works.

If I modify the Qsys config at all, even something really simple like add another (unused) slave to the MM bridge, the ARM hangs when I configure the FPGA (over USB blaster). If I make my own system from scratch, it hangs the ARM. Pretty much if I do anything at all other than the unmodified demo DE10_NANO_SoC_GHRD, it hangs the ARM on configuration.

I don’t think this is a problem with U-boot config, since the demo works great. I’m not accessing new HPS components or anything. Really just adding another slave to the Avalon MM bridge, and that hangs everything.

I think I’ve now spent four solid weekends on this problem. Any ideas? Thank you!


If I pipe the bridge to a PIO (bridge master -> PIO slave), it works fine. So I think the problem is that I’m trying to expose the bridge’s master into my own code (by exporting it) and this is causing the hang. Is that plausible? As far as I can tell, I’m implementing a simple Avalon MM slave properly in my main Verilog module. I can’t find examples of how to export an Avalon master back into Verilog for handling. Can anyone point me in the right direction?

Hello @lkesteloot,
do You not forget to recompile the preloader (i.e. part of U-Boot) to reflect changes done in QSys? It seems me that this would be the source of problém according to Your description.
Best wishes.
Yours sincerely
Jan Konecny.