Bought DE10-Nano Kit several days ago. This is my first SoC board. What confusing is seeing DDR3 signals in FPGA project. I believe DDR3 is initialized and used on HPS side, so it should provide all necessary connections to DDR3. FPGA, from my understanding should use bridge through HPC to access memory. DDR3 chip is physically a single device, how both HPC and FPGA can have separate sets of DDR3 signals? They should compete each other, isn’t?
Those DDR3 signals are for the HPS part of the device only.
- If those DDR3 signals are simple wires from DDR3 chip to HPS memory controller, then it’s wrong… HPS works with DDR3 without FPGA part.
- if thise DDR3 signals are wires from FPGA to HPS then it’s also wrong because FPGA is connected by MPFE interface which is completely different.
So, it’s still unclear the purpose of those signals.
HPS IP core has many DDR3 timings settings which shouldn’t be there since HPS initializes and control the DDR3. Basically HPS IP core shouldn’t have any DDR3 signals and settings, except MPFE settings.
Actually i have big problem with my FPGA project. I use DDR3 memory for VIP cores. When i upload core through JTAG (or even through linux command line) there is a high chance it won’t work. But it starts to work when i press reset (cold or warm - doesn’t matter). It looks like DDR3 controller hangs at FPGA initializing stage. If i don’t use DDR3 IP core, then everything works fine.
This is very bad news for me because my project requires change the FPGA cores at runtime…
OK please be specific about where you are seeing the DDR3 signals.
i’m talking about input/output signals of top-level module:
output [14:0] HPS_DDR3_ADDR, output [2:0] HPS_DDR3_BA, output HPS_DDR3_CAS_N, output HPS_DDR3_CKE, output HPS_DDR3_CK_N, output HPS_DDR3_CK_P, output HPS_DDR3_CS_N, output [3:0] HPS_DDR3_DM, inout [31:0] HPS_DDR3_DQ, inout [3:0] HPS_DDR3_DQS_N, inout [3:0] HPS_DDR3_DQS_P, output HPS_DDR3_ODT, output HPS_DDR3_RAS_N, output HPS_DDR3_RESET_N, input HPS_DDR3_RZQ, output HPS_DDR3_WE_N,
P.S.: i’ve just tried not to connect these signals to soc_system module and to my surprise, my FPGA core is still working! I’m using VIP components. DDR3 is used for frame buffers.
So. these signals are basically not used. But it requires to remove hps_sdram_p0.sdc to make fitter happy, which is not good because other used signals may loose their constraints.
I want to use the bare metal project. From my QSYS under hardprocessor I don’t want to export the DDR3 signals settings or atleast don’t want to use it.
Is it possible to still use the DDR3 directly from ARM processor?
If yes how can we configure the Contol registers of the DDR3?
Is there any tool like DAVE?
On which address range i have to write inorder to configure the DDR3 configuration registers?
How can i do the clock settings and the other timing settings of the DDR3 if i don’t want to use QSYS HARDPROCESSOR SDRAM settings?
I will be waiting for the reply.
thanks in advance.