Hi all,
I am working on a project aims to implement custom neural network on FPGA an operate it using the Linux system. It will work on video captured by webcam connected to the USB. It should recognize certain objects in the video depending on its training. the used kit is DE10-Nano.
I need help regarding the steps i should follow to to accomplish the project in shortest time possible.
- How the the Linux system will send the data to the NN on the FPGA?
-should i use QSys?
-will i need the SOC ESD in any phase?
-will the webcam need drivers?
I am experienced some how with RTL coding, FPGA, and Linux. But this is my first time with the SOC design flow.
I appreciate any help
Regards,
M.Abdelshakour
Go and do the tutorials for your board. DE1-SoC has step by step examples on how to move data from processor and HPS.
Then go and read the Handbook of your chip to understand how the FPGA is seen by processor. Basically the FPGA is mapped in the address space of the HPS. So you have 2 options to move data to the FPGA. One is to use mmap (like in the tutorials for your board) and once you have a virtual address representing the FPGA you use that address and pointers to move data like any other peripheral. You can also use memcpy that is a standard function to move blocks of data and its faster that using pointers inside a for loop.
Other option is to use DMA in the HPS. I have an example here:
Aswering to your Questions:
-yes you have to use Qsys. In Qsys you add the HPS, otherwise it is inactive. And using Qsys you connect your custom logic to the processor. First you have to do a memory maped slave in VHDL and debug it through simulation. Then do a Qsys component from it to be able to connect it using Qsys. The connect your component and the HPS in Qsys. There are tutorials on how to do all that. Its impossible to explain here.
-yes you need the SoC EDS. It install the compilers for HPS. Using the SoC EDS you can compile the C/C++ for the processor. You can also use the DS-5 that is optionally installed after installing the SoC EDS.
-about the drivers I dont know. you have to connect it and see if thats possible.
Regards!
This is a great response, but I’m not sure where to find those tutorials you mention, in particular “DE1-SoC has step by step examples on how to move data from processor and HPS” - that is exactly what I need. I’m using DE10-nano, but as mention, should not matter.
A link would be super cool!
We recently developed a CNN accelerator based on the OpenCL framework. We used DE10 Nano based on Intel Cyclone V SoC FPGA for the implementation.
You can check out the entire design flow to implement the accelerator and the relevant codes in the following repository: https://github.com/tirumalnaidu/opencl-cnn-accelerator
For more technical information, refer to this presentation: Link