I have a Platform Designer Qsys that appears as follows.
I am playing around in the u-boot console. I am trying to write to SDRAM via the FPGA path then read it back via the Cortex’s direct path to the SDRAM. This involves programming an offset into the address extender in the FPGA then writing to some address within the window. Then after, that ideally you would read the corresponding SDRAM address with the Cortex A9. This does not appear to working. Addressing from the point of view is different from the perspective of the FPGA2SDRAM interface and the Cortex A9 address space. I am trying to understand the difference in address mapping between the two.
=> mw FF220000 00000000 => mw FF220004 20000000 => mw FF210000 deadbeef => md FF210000 1 ff210000: deadbeef .... => md 20000000 1 20000000: ee6fa4f9 ..o.