Cyclone V DE10-NANO: Not able to boot to Linux kernel using u-boot.scr

Hi everyone.

I am following this guide to build the bootloader and Linux kernel.

Then I change the following files in order to load the u-boot.scr:
u-boot-socfpga/include/configs/socfpga_common.h

#ifndef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS
“fdtfile=” CONFIG_DEFAULT_FDT_FILE “\0”
“bootm_size=0xa000000\0”
“kernel_addr_r=”__stringify(CONFIG_SYS_LOAD_ADDR)"\0"
“fdt_addr_r=0x02000000\0”
“scriptaddr=0x02100000\0”
“pxefile_addr_r=0x02200000\0”
“ramdisk_addr_r=0x02300000\0”
“socfpga_legacy_reset_compat=1\0”
“scriptfile=u-boot.scr” “\0”
“fpgadata=0x2000000” “\0”
“callscript=fatload mmc 0:1 $fpgadata $scriptfile;”
“source $fpgadata” “\0”
BOOTENV

u-boot-socfpga/include/config_distro_bootcmd.h

#define CONFIG_BOOTCOMMAND “run callscript”

And my u-boot.scr

echo – Programming FPGA –

fatload mmc 0:1 $fpgadata soc_system.rbf;
fpga load 0 $fpgadata $filesize;

#enable HPS-FPGA, FPGA-HPS bridge
bridge enable;

#set up env variable
setenv fdtimage soc_system.dtb;
setenv bootimage zImage;

setenv mmcroot /dev/mmcblk0p2;
setenv bootargs console=ttyS0,115200 root=${mmcroot} rw rootwait;

echo --1–
mmc rescan;
fatload mmc 0:1 ${loadaddr} ${bootimage};
echo --2–
fatload mmc 0:1 ${fdt_addr_r} ${fdtimage};
echo --3–
bootz ${loadaddr} - ${fdtaddr};

but it cannot boot to Linux kernel

U-Boot SPL 2019.04 (Jul 24 2020 - 23:48:07 +0900)
Trying to boot from MMC1

U-Boot 2019.04 (Jul 24 2020 - 23:48:07 +0900)

CPU: Altera SoCFPGA Platform
FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
BOOT: SD/MMC Internal Transceiver (3.0V)
Watchdog enabled
DRAM: 1 GiB
MMC: dwmmc0@ff704000: 0
Loading Environment from MMC… OK
In: serial
Out: serial
Err: serial
Model: Altera SOCFPGA Cyclone V SoC Development Kit
Net:
Error: ethernet@ff702000 address not set.
eth-1: ethernet@ff702000
Hit any key to stop autoboot: 0
588 bytes read in 3 ms (191.4 KiB/s)
## Executing script at 02000000
– Programming FPGA –
’ - try 'help’d ’
2081456 bytes read in 105 ms (18.9 MiB/s)
’ - try 'help’d ’
’ - try 'help’d ’
’ - try 'help’d ’
’ - try 'help’d ’
’ - try 'help’d ’
’ - try 'help’d ’
’ - try 'help’d ’
’ - try 'help’d ’
’ - try 'help’d ’
’ - try 'help’d ’
’ - try 'help’d ’
–1--
’ - try 'help’d ’
5083880 bytes read in 260 ms (18.6 MiB/s)
’ - try 'help’d ’
–2--
26612 bytes read in 3 ms (8.5 MiB/s)
’ - try 'help’d ’
–3--
FDT and ATAGS support not compiled in - hanging
### ERROR ### Please RESET the board ###

Hey
I had same issues.
I think your FPGA config cmd is wrong.
Try this guide: https://github.com/robseb/HPS2FPGAmapping#2-part-building-of-the-primary-bootloader-with-intel-eds
That should help.

Thanks robseb

I could load the rbf file and linux with no problem using EDS 18.1, but if I do it at EDS 20.1, I get this error.

Thanks