Cyclone V FPGA Configuration per HPS ineffective (no error indication)

Dear All,

I am working on a Terasic DE0_NANO_SOC board (Cyclone V) using

1a) UBOOT to read an rbf-file and do an fpga_load from SDCARD
1b) LINUX Kernel 3.13 to read an rbf-file and write it to /dev/fpga0
1c) Altera Quartus 16
1d) When I configure the FPGA from JTAG the user function is there and
GPIO is functional.
1e) I use internal oscillator as configuration clock
1f) MSEL to 00100
(FPP 16 , No compression and slow POR)

The FPGA image I created lets one LED (directly connected to FPGA GPIO) blink or statically set it.

Regardless whether I use my own u-boot or factory one (from TERASIC)
I can see configuration done LED turns on (after a short pulse),
no error indication whatsoever and peeking the fpga manager
registers indicate FPGA is in user mode.

But I seems the FPGA does not really work. No user function could be discovered (not even straigt forward LED settings).

After starting the Linux kernel, the Image in the FLASH is loading so I cannot really update the FPGA per SW as it appears to be overwritten or somehow
not really ending up.

2a) I removed reset-request from FPGA to HPS -> No Change
2b) I changed config clock to DCLK -> No Change
2c) I created different SDCARD images from Terasic just to test SW loading
-> Always inactive FPGA

2d) Can this be a reset-issue or clock-manager issue?

Any help on this appreciated!

Do you get any indication in u-boot of whether the FPGA programmed correctly? I am having trouble programming my CycloneV from u-boot using the DE1-SoC board. I have a sneaking suspicion there may be a bug in branch socfpga_v2019.04 or that the feature to program CycloneV FPGA simply does not exist.