Hi, I’m trying to display something via VGA on linux system without desktop (the final goal is to launch Qt app writing to /dev/fb). I’m confused about how to instantiate Frame Buffer II (alt_vip_cl_vfb) in the device tree, and the main problem is the reg property. This is my qsys project which compiles without errors.
Primarily, I don’t know what the size should be, but I’m not sure about the address too. I assume that it would be something like reg = <0x30000000 correct_size>;. To me, as I’m a newbie, the documentation of Frame Buffer is poor.
The second problem is that I’m confused about mapping FPGA masters connected to FPGA-to-HPS bridge. Is the address 0x30000000 correct, regarding that RAM ranges from 0x0 to 0x40000000 ?
I can’t find any example of using Frame Buffer II on Cyclone V SoC with Linux.
I’m asking for help.
I’m struggling to find the source code for the driver, else I might be able to give you some idea.
I found this https://lwn.net/Articles/729768/
which calls out
drivers/gpu/drm/ivip/
but I can’t find that anywhere in linux-socfpga source
nor the official kernel
Did a little digging and ended up here
which led me here
Pretty esoteric piece of documentation, but maybe that can help you?
Looks to be from March, so reasonably updated?
If that doesn’t work, this probably isn’t what you want to hear (since it sounds like you may be more firmware side than software), but you can always write your own driver. Should be able to look through the register space and allocate buffers using dma_alloc_coherent. I’m writing my own framebuffer IP right now and could give you some code for how to allocate the buffers if you need it. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_vip.pdf#page=160&zoom=100,0,612
Thank you @jackfrye11 for suggestions and some explanation. You helped with the addresses for sure, but unfortunately it still doesn’t work. I made some changes since last time. I connected control registers to lightweight HPS-to-FPGA bridge at offset 0 - so the base address is ff200000 - and I configured framebuffer IP as Frame Reader only.
This is the current qsys project:
For your Platform Designer design, is the framebuffer IP mem_master_rd interface supposed to be hooked up to the f2h_axi_slave (whose address space I think links you into a number of different things inside the chip) or is it supposed to be one of the f2h_sdram_* interfaces which go directly to the memory controller for the RAM? For my own framebuffer IP, I was connecting it to FPGA2SDRAM interfaces. What does the address map of the FPGA2HPS interface look like? Is there a way to get to the SDRAM going through that address space?
Looks like you hit some issue in your log where you were transacting from a space you shouldn’t have. If you FPGA2HPS allows you to play with chip settings and peripherals, I could easily see how you might hang the chip/trip the watchdog. Do you know how to use SignalTap? What is going on on the mem_master_rd bus right before that kernel seg fault?
Hi,
I finally got it working. The problem presented previously (with memory allocation during kernel module initialization) disappeared when I switched to linux 5.4-lts version - I had been using 5.12 or 5.11 before. Then I read IP’s documentation more carefully and I realized that another blocks are needed. Now I have to generate SDK for Qt in Yocto and try to write some app.
Frame Buffer IP works fine with both interfaces ( FPGA2HPS bridge and f2h_sdram_*).
Current Platform Designer project looks like this (maybe it will help someone):