Cyclone V HPS - Maximum frequency only 200 BogoMIPS

Hello,

I am trying to figure out why in /proc/cpuinfo I have only 200 BogoMIPS as the maximum CPU frequency:

processor       : 0
model name      : ARMv7 Processor rev 0 (v7l)
BogoMIPS        : 200.00
Features        : half thumb fastmult vfp edsp thumbee neon vfpv3 tls vfpd32
CPU implementer : 0x41
CPU architecture: 7
CPU variant     : 0x3
CPU part        : 0xc09
CPU revision    : 0

processor       : 1
model name      : ARMv7 Processor rev 0 (v7l)
BogoMIPS        : 200.00
Features        : half thumb fastmult vfp edsp thumbee neon vfpv3 tls vfpd32
CPU implementer : 0x41
CPU architecture: 7
CPU variant     : 0x3
CPU part        : 0xc09
CPU revision    : 0

Hardware        : Altera SOCFPGA
Revision        : 0000
Serial          : 0000000000000000

The content of /sys/kernel/debug/clk/clk_summary is:

                                 enable  prepare  protect                                duty  hardware
   clock                          count    count    count        rate   accuracy phase  cycle    enable
-------------------------------------------------------------------------------------------------------
 osc1                                 5        5        0    25000000          0     0  50000         Y
    sdram_pll                         0        0        0   800000000          0     0  50000         Y
       h2f_usr2_clk                   0        0        0   133333333          0     0  50000         Y
          h2f_user2_clk               0        0        0   133333333          0     0  50000         ?
       ddr_dq_clk                     0        0        0   400000000          0     0  50000         Y
          ddr_dq_clk_gate             0        0        0   400000000          0     0  50000         ?
       ddr_2x_dqs_clk                 0        0        0   800000000          0     0  50000         Y
          ddr_2x_dqs_clk_gate         0        0        0   800000000          0     0  50000         ?
       ddr_dqs_clk                    0        0        0   400000000          0     0  50000         Y
          ddr_dqs_clk_gate            0        0        0   400000000          0     0  50000         ?
    periph_pll                        3        3        0  1000000000          0     0  50000         Y
       h2f_usr1_clk                   0        0        0    50000000          0     0  50000         Y
          h2f_user1_clk               0        0        0    50000000          0     0  50000         ?
       per_base_clk                   3        3        0   200000000          0     0  50000         Y
          gpio_db_clk                 0        0        0       32000          0     0  50000         ?
          can1_clk                    0        0        0    40000000          0     0  50000         ?
          can0_clk                    0        0        0    40000000          0     0  50000         ?
          spi_m_clk                   0        0        0   200000000          0     0  50000         ?
          usb_mp_clk                  1        1        0   200000000          0     0  50000         ?
          l4_sp_clk                   3        3        0   100000000          0     0  50000         ?
          l4_mp_clk                   1        1        0   100000000          0     0  50000         ?
       per_nand_mmc_clk               1        1        0   200000000          0     0  50000         Y
          nand_x_clk                  0        0        0   200000000          0     0  50000         ?
             nand_clk                 0        0        0    50000000          0     0  50000         ?
             nand_ecc_clk             0        0        0   200000000          0     0  50000         ?
          sdmmc_clk                   1        1        0   200000000          0     0  50000         ?
             sdmmc_clk_divided        1        1        0    50000000          0     0  50000         ?
       per_qsi_clk                    0        0        0     1953125          0     0  50000         Y
       emac1_clk                      1        1        0   250000000          0     0  50000         Y
          emac_1_clk                  1        1        0   250000000          0     0  50000         ?
       emac0_clk                      0        0        0     1953125          0     0  50000         Y
          emac_0_clk                  0        0        0     1953125          0     0  50000         ?
    dbg_base_clk                      0        0        0     6250000          0     0  50000         Y
       dbg_timer_clk                  0        0        0     6250000          0     0  50000         ?
       dbg_trace_clk                  0        0        0     6250000          0     0  50000         ?
       dbg_at_clk                     0        0        0     6250000          0     0  50000         ?
          dbg_clk                     0        0        0     3125000          0     0  50000         ?
    main_pll                          2        2        0  1600000000          0     0  50000         Y
       cfg_h2f_usr0_clk               0        0        0   100000000          0     0  50000         Y
          h2f_user0_clk               0        0        0   100000000          0     0  50000         ?
          cfg_clk                     0        0        0   100000000          0     0  50000         ?
       main_nand_sdmmc_clk            0        0        0     3125000          0     0  50000         Y
       main_qspi_clk                  0        0        0     3125000          0     0  50000         Y
          qspi_clk                    0        0        0     3125000          0     0  50000         ?
       mainclk                        1        1        0   400000000          0     0  50000         Y
          l3_mp_clk                   0        0        0   200000000          0     0  50000         ?
             l3_sp_clk                0        0        0   100000000          0     0  50000         Y
          l3_main_clk                 0        0        0   400000000          0     0  50000         Y
          l4_main_clk                 3        4        0   400000000          0     0  50000         ?
       mpuclk                         1        1        0   800000000          0     0  50000         Y
          mpu_l2_ram_clk              0        0        0   400000000          0     0  50000         Y
          mpu_periph_clk              1        1        0   200000000          0     0  50000         Y

I am using the latest linux-socfpga kernel.

Somebody probably solved it on the Intel forum here, only stating that he had to change clocks/PLL section in some DTS file based on some information from version v4.14 of the kernel github repository, but didn’t provide any details and I am struggling to find the information there.

Does anybody know what changes must be made to get 1594.16 BogoMIPS (as shown in the forum post)?

Thanks for any help.