I am working on two differen Boards with two different FPGA Load Msel configurations.
During Boot-Up in Uboot, a read out of the fpgamgrregs Address is required in order to see whether an encrypted or raw fpga binary file can be loaded into the FPGA.
This happens if i Run the command:
=> md 0xFF706000
ff706000: 00000060 00000200 00000000 00000000 `…
data abort
pc : [<3ffbc5e4>] lr : [<3ffbc5f7>]
reloc pc : [<0104d624>] lr : [<0104d637>]
sp : 3bf67d90 ip : 00000000 fp : 00000004
r10: 00000003 r9 : 3bf6cec0 r8 : ff70601c
r7 : 00000004 r6 : 3bf67e34 r5 : 00000004 r4 : 00000004
r3 : 3bf67e2b r2 : 00000008 r1 : 3ffcf51e r0 : 00000009
Flags: nZCv IRQs off FIQs off Mode SVC_32 (T)
Code: e8bd 8df0 2d04 d10e (f8d8) 3000
Resetting CPU …
resetting …
Why does my CPU reset? It makes it very difficult to keep the information… is there an option where the board does not get resetted?
Thanks in advance!