Cyclone V SoC Development kit

I’m currently using the Cyclone V SoC Development kit. I’m using this board to generate 3 different 300MHz clocks. I’m trying to use the HSMC port (with a HSMC-SMA adapter board). Based on the information in the schematics, the HSMC port must be connected to the transceivers(bank 2BL on the FPGA).

I’m assigning HSMC_TX_P1 to Pin_H4 of the FPGA. Similarly, other pins will follow. However, when I compile, I keep getting error messages regarding bank B2L not being able to support the required termination setting.

“Error (169033): I/O pin HSMA_TX_P4 with Termination logic option setting Series 50 Ohm without Calibration cannot be placed inside I/O Bank B2L because the I/O bank does not support the requested Termination setting”

I have changed the I/O standard to LVDS, 1.5PCML and all others in the list. I keep getting the same errors. Does this mean that transceivers on the Cyclone V SoC cannot actually be used using the HSMC interface?