Cyclone V soc secure boot example

I have been working on a secure boot on the Cyclone V, and to that end got the DE10-nano board, and am trying to implement the cyclone V soc secure boot example


I have, I believe, followed the instructions correctly, however, the interesting part of the boot is failing. That is, I generated a uboot payload, signed it, and then burned the signature and the payload as part of the JIC file. When the system boots, I get the following:

U-Boot SPL 2013.01.01 (Dec 16 2021 - 11:16:14)
BOARD : Altera SOCFPGA Cyclone V Board
CLOCK: EOSC1 clock 25000 KHz
CLOCK: EOSC2 clock 25000 KHz
CLOCK: F2S_SDR_REF clock 0 KHz
CLOCK: F2S_PER_REF clock 0 KHz
CLOCK: MPU clock 800 MHz
CLOCK: DDR clock 400 MHz
CLOCK: UART clock 100000 KHz
CLOCK: MMC clock 50000 KHz
CLOCK: QSPI clock 3125 KHz
SDRAM: Initializing MMR registers
SDRAM: Calibrating PHY
SEQ.C: Preparing to start memory calibration
SDRAM: 1024 MiB
INIT: MPL build: Oct 6 2021 09:44:47
INIT: Initializing board.
INIT: MPU clock = 800 MHz
INIT: DDR clock = 400 MHz
INIT: Initializing successful.
SBOOT: Auth Fail - Error 6

And of course at this point it does not run the uboot, rather it hangs. I followed the code to see what the issue is, and I get this:

Calling stack of failure:

*** authenticate_ecdsa256_signature**
*** mbedtls_ecdsa_read_signature**
*** mbedtls_ecdsa_verify**

In mbedtls_ecdsa_verify, which is what failed, this is the line which failed
* Step 8: check if v (that is, R.X) is equal to r
if( mbedtls_mpi_cmp_mpi( &R.X, r ) != 0 )
goto cleanup;

Now, the signature and the uboot payload were both generated by the process as shown in step 2 of the demo, that is:

2. Generation and signing of the next stage boot loader

  1. Generate the payload executable. In our case this will be u-boot, so that will be generated next. In an embedded command shell, move to the software/spl_bsp directory and execute “make uboot” to generate a u-boot executable file.
  2. Sign and package the payload executable ready for storing in flash memory by changing to the software/uboot_payload directory and executing “./”

I did exactly that, and in fact, after receiving the error, went and verified that both the signature and the signed payload were correctly burned (by doing memory dumps and comparing them to the original hex files generated in step 2).

A few other issues which may help pinpoint the problem. When simply powering on the board without using the debugger, no serial output at all happens. In order to get as far as I have, and see the AUTH Fail, I had to connect the debugger and run from HPS start. I expect I have some issue with waiting for the FPGA as well, and perhaps it is connected.

Has anyone experienced the same thing, or have an idea why this could be happening?

I have tried the same tutorial and did get all of the steps to succeed. Including getting serial output without use of the debugger. What are you using for serial output?

One thing that’s different between the tutorial and most recent boards is the size of the epcs flash. Tutorial assumes a different size than is actually located on the board. Also the tutorial was just moved into the trash space for some reason.

I’ve hooked a USB cable to a Windows PC running PUTTY to the serial output. It’s the correct one, because if I run through the debugger it gives the serial output shown above.

I changed the size of the flash to make it burnable (ECPS 128 rather than 64).

I’ve been answered by Intel that secure boot is no longer supported by the Cyclone V, which is why I expect the tutorial was trashed.

Yeah I saw the post on the intel forum. While I managed to reproduce the tutorial for the de10 nano using their exact recommended software versions we have just switched to a de10 standard for another test and are currently running into the issue that we are not getting any console output. Debugger will be the next step for us as well.

Unfortunately I do not have any clear ideas as to why your verification is failing.

I checked the output and I see a lot less logging output. And it matches the tutorial more closely. Did you enable some additional logging?

INIT: MPL build: Oct 25 2021 09:58:47
INIT: Initializing board.
INIT: MPU clock = 800 MHz
INIT: DDR clock = 400 MHz
INIT: Initializing successful.

U-Boot 2013.01.01 (Oct 25 2021 - 11:29:04)

Not that I know of… as far as I can tell, by looking at the sources, the other printouts are coming from spl_board_init, which is calling cm_print_clock_quick_summary() which is under the #ifdef CONFIG_SPL_SERIAL_SUPPORT which is defined in socfpga_common.h. Someone on the Intel board pointed out that it seems that the order of the boot looks incorrect, but I cannot see how it would have happened. Right now I am unable to check this, as my card is with the local Intel rep, who borrowed it to attempt to build the demo on Linux (we use Windows) to see if we managed to get a better result, but so far no luck. We actually did it together, (I was home sick and we did it on his machine while sharing screens). As soon as the card is back, I will give you some better answers if I can.

I hope you guys have more luck on linux. Most steps of the tutorial especially the soceds / preloader compilation stuff was also done by us on linux.

We managed to get our de10 standard board running with a boot from fpga preloader as well and are currently waiting on our own boards before we will do additional experiments related to secure boot. But i’ll keep an eye on this topic.