Right. That is fine.
You should be able to build u-boot-with-spl.sfp so that you can get through the SPL, which is working fine as far as I can tell.
Then you should be able to point u-boot to a script that contains commands to interface with the FPGA manager in order to load a CycloneV FPGA image off of the SD Card or out of SPI Flash and program it into the FPGA
fatload mmc 0:1 ${fpgadata} socfpga.rbf;
fpga load 0 ${fpgadata} ${filesize};
bridge enable;
Right now, I can not do this and I do not know anyone on this forum who has. Back at Christmas time, I emailed Tom Rini, who at that time had the latest u-boot commits to socfpga_cyclone5_defconfig, detailing the issues and asking for guidance. He never got back to me, nor has anyone been able to program CycloneV FPGA from u-boot since this new build flow came out.
To date, my best investigation has led me here GSRD v13.1 - Programming FPGA from HPS | Documentation | RocketBoards.org, which details that the -6 error code I receive every time I try to program the FPGA is due to “The FPGA is having timeout from entering init phase or user mode after disable AXI configuration at FPGA Manager”. Perhaps I am configuring the HPS incorrectly in my Quartus build, but I believe I once configured the HPS the same way it is documented in this excellent guide from some former Cornell undergrads https://people.ece.cornell.edu/land/courses/ece5760/DE1_SOC/SoC-FPGA%20Design%20Guide_EPFL.pdf and I was able to program the FPGA from u-boot using the old flow with separate SPL and u-boot
Although I am just a hobbyist on the Intel platform, it seems to me like there is a bug and no one with the expertise to date has been able to offer insight on this forum.