Hello, I am currently doing my project which requires me to use DE1-SoC.
The project is to perform bearing health’s prognostic, it includes 3 parts which are: feature extraction, linear regression, and remaining useful life estimation using polynomial regression.
What I have is the Python code for the above 3 functions, and I want to perform feature extraction on the FPGA side.
The general idea is the dataset goes into HPS, then send to FPGA for feature extraction, and send the result back HPS to perform the other 2 functions.
The objective is to reduce the processing time as feature extraction will take the most time to process.
My question is: is it possible?
Because so far the tutorial I found, the C or C++ language is used in HPS to communicate with FPGA, I cant find any which uses Python.
If it is possible, how can it be done?
I have tried a few tutorials to understand the HPS-FPGA communication but maybe my version of Quartus Prime is not the same with the tutorials, some steps were missing and took me quite a while to google them and troubleshoot, and at the end, I managed to get the output as stated in the tutorial but I can’t understand how I did it. Previously I only use Quartus Prime to write Verilog for FPGA only, and I still consider myself a totally newbie to Platform Designer(formerly as Qsys) even though I have tried a few tutorial.
So I would really need someone to enlighten me.
Or is it more ideal to just use HPS to perform all the things?
Thank you!
Hi,
I think that you need first do a tutorial about Platform Designer tool like:
Sahand Kashami-Akaharma
Other tool that it is also interesting is OpenCL for hw/sw codesign
https://software.intel.com/en-us/articles/opencl-tutorials
What is your board , FPGA and Quartus version?
Regards
Cándido
If you want to use linux as your OS in HPS you can see the FPGA as another device that needs to be mapped in order to get access to it.
have a look on these:
BR,
Hi!
first of all thanks for replying.
And sorry for leaving this thread not replied for so long because I was refining the python code for my project at the same time learn and do more tutorials about Qsys.
@Mikernl Thanks for posting the links! I have tried the CycloneV HPS FIFO. However I am still not quite get how it works actually. I managed to get the results after following the instruction. But I wish to know how exactly how the data being transfer from HPS to the FPGA, and after some work and how the FPGA send back the data to HPS. Because what I can understand from the tutorial is just control the FPGA peripherals such as LEDs from HPS side… But I am going to send dataset in .txt to fpga and send back to HPS after work done in FPGA…
I haven’t try the tutorial in the second link you shared, hopefully can get some insight from there…
@candido Thanks for posting the links! After doing a few tutorials about Qsys, I have some rough idea on how it works.
And I found that OpenCL seems very popular for people who tend to use FPGA as an accelerator. I I haven’t really read about OpenCL because I am focusing on Qsys, afraid not enough time for me to learn OpenCL.
Hi, actually i don’t know much about this architecture CycloneV i wanted to buy the board but i don’t have much time right now… maybe in a couple of months… back to your question on how things works… when i was doing my internship i worked with the Zedboard which is something similar to this architecture SoC with FPGA + ARM back then when i was trying to understand how this 2 worlds interact i needed to understand how actually bus AXI works i’m not sure if Altera is using this bus to communicate HPS with FPGA but they probably using am AXI-kind-of bus for that… anyway, whatever they use, it is a bus so it works “just like” your PCI in your PC and linux have a hole infrastructure to handle bus controllers… you’ll probably need to read more about the Device Model in Linux.
br,
Hi,
in case you run embedded Linux on the HPS it is no problem to use Python for interacting with the FPGA. However, in same cases it is better to use a C++ application based on a better performance.
I designed an open source embedded Linux and a I wrote guides that can answer your questions.
Please look:
I hope I can help you,
Robin
In case use need a NIOS II Processor with FreeRTOS: