DE1-SoC Unpopulated JTAG header

1

Before I blow my board up I just thought I’d check something with the more hardware minded folks out there.

According to the DE1-SoC schematic provided by Terasic, pin 2 of this header has a 10k pullup and is labeled USB_DISABLE_n, so presumably when tied to ground this disables the USB-Blaster interface and routes TDI/TDO etc to this header. That seems clear from the schematic.

As I’m using the free version of DS-5 from Quartus I can’t do baremetal JTAG as the free licence doesn’t allow it.
My thinking is to solder a right-angled 10 pin header onto the board and use a standard Eclipse/CDT/ARM-cross compiler setup for baremetal JTAG.

My question is, will a connected JTAG-Blaster cable ground this pin or do I need to short it to pin 10 - also a GND.

Thanks people.

2

Why do you need the other pin header ?

I have tried eclipse/arm-embeded/openocd/usb-blaster2(normal way), but
I could not halt core1. This problem might block eclipse programming. I think this issue came from openocd does not have any fpga dap impliment c code compared to Zynq. But I’m not sure. I would like to know why and fix.

So now I think I have to looking for the other debugger, such as J-Link.
In this case, I might have to solder new header for J-link.