DE10-Nano U-boot-socfpga: Enable bridges lwhps2fpga

Hi,

As described in the below link managed to compile the v2018.05 version of u-boot.


Source From:

Upon completing the boot, all three bridges are registered.

dmesg |grep 2fpga
[ 1.090025] altera_hps2fpga_bridge sopc@0:fpgabridge@0: fpga bridge [hps2fpga] registered
[ 1.098459] altera_hps2fpga_bridge sopc@0:fpgabridge@1: fpga bridge [lwhps2fpga] registered
[ 1.106976] altera_hps2fpga_bridge sopc@0:fpgabridge@2: fpga bridge [fpga2hps] registered

But i see that they are disabled by default:

cat /sys/class/fpga_bridge/br*/state
disabled
disabled
disabled
disabled

Corresponding Bridge names:

cat /sys/class/fpga_bridge/br*/name
hps2fpga
lwhps2fpga
fpga2hps
fpga2sdram

After kernel boot and running application code, the LWHPS2FPGA accesses are resulting in Bus Error as below:

[ 271.701829] Unhandled fault: external abort on non-linefetch (0x818) at 0xb6085004
[ 271.709377] pgd = ee7a0000
[ 271.712075] [b6085004] *pgd=3fceb831
Bus error

Two questions:

  1. How to enable these bridges : hps2fpga, lwhps2fpga, fpga2hps, fpga2sdram ?
  2. Does this enabling to be done during U-boot or can it be handled by application after Linux kernel boot?

CC:Requesting @rafael_Mello to comment.

Using the GHRD DTB from the Golden Reference Design (with u-boot v2018.05)

cat /sys/class/fpga_bridge/br*/name
hps2fpga
lwhps2fpga
fpga2hps
fpga2sdram
cat /sys/class/fpga_bridge/br*/state
disabled
disabled
disabled
disabled
cat /proc/device-tree/model
Terasic DE10 NANO

Using u-boot v2013.01, these bridges are enabled after u-boot

cat /sys/class/fpga_bridge/br*/name
hps2fpga
lwhps2fpga
fpga2hps
fpga2sdram
cat /sys/class/fpga_bridge/br*/state
enabled
enabled
enabled
enabled
cat /proc/device-tree/model
Terasic DE10 NANO

The best reference to enable these bridges in U-Boot i found below: