Error in make-all commad, Building the GSRD of Stratix 10 SoC L-tile

[Abbas]

Hi RocketBoards,
We’re working on Ubuntu 20.04.6 LTS and Quartus Prime Pro Edition 23.1

We followed the Building Hardware procedure from here:

Stratix 10 SoC L-Tile GSRD

We downloaded the compiler tool-chain, and added it to the PATH variable. Hence, we created the environment with no errors.

Building the Hardware Design

In this step, we successfully build project using this command
~/intelFPGA_pro/23.1/nios2eds/nios2_command_shell.sh make generate_from_tcl

But, the last command which is “make all” we got error in it
~/intelFPGA_pro/23.1/nios2eds/nios2_command_shell.sh make all
Here, is the terminal snap of error**

Kindly, go through it why this error occurs in the “make all” command.
Abbas Ali
FPGA Engineer

[Raju]

Hi Abbas Ali,

Based on the error i can suggest you following ways

1)Make sure the system requirement (RAM) should be high.
2)Restart the system and try to build the hardware design.
3) Check the values for the below mentioned parameters in the Makefile
a)QUARTUS_DEVICE
b)FPGA_device
c)HPS_ENABLE_SGMII
d)ENABLE_PARTIAL_RECONFIGURATION
e)ENABLE_NIOSV_SUBSYS
f)ENABLE_HPS_EMIF_ECC
4)Make sure the quartus license is linked and updation of below parameter
a)LM_LICENSE_FILE

Follow the system requirement mentioned in the intel website for Startix 10.

Thanks & Regards
Raju S

[Abbas]

Hi Raju,

Hope, you will be fine and well.

My PC Specifications:

• CPU: Intel(R) Core™ i7-4790 CPU @ 3.60GHz
• RAM: 16 GB
• Storage: 500 GB SSD

Despite restarting the PC several times, we were unable to build the hardware design.
Taking care of the Quartus license and updating the following parameters is the solution you told me to do
a)LM_LICENSE_FILE
Therefore, it has already been completed. Here is the snap

Here, is the mentioned parameters values in the Makefile
HPS_ENABLE_SGMII ?= 1
ENABLE_PARTIAL_RECONFIGURATION ?= 1
ENABLE_PARTIAL_RECONFIGURATION_TESTING ?= 0
ENABLE_HPS_EMIF_ECC ?= 1
ENABLE_FPGA_I2C ?= 0

QUARTUS_DEVICE_FAMILY := Stratix\ 10
QUARTUS_DEVICE ?= 1SX280LU2F50E2VG

Let me know, if you found this information well and provide me the possible solution for it.

Thanks

Abbas Ali
FPGA Engineer

[Abbas]

Hi Raju,

Hopefully, the above issues solved.

Now, it gives an error in this statement. Here is the snap

Why, the ghrd_1sx280lu2f50e2vg.sof file does not exists in the output_files directory?

Thanks
Abbas Ali
FPGA Engineer

[Raju]

Hi Abbas Ali,

Thanks for the reply.

As per snap shared by you, there is a issue with license linking.

Before make all command, give the following commands

export LM_LICENSE_FILE= License path
export QUARTUS_DEVICE=1SX280LU2F50E2VG
export FPGA_device=1SX280LU2F50E2VG
export HPS_ENABLE_SGMII=0
export ENABLE_PARTIAL_RECONFIGURATION=0
export ENABLE_NIOSV_SUBSYS=0
export ENABLE_HPS_EMIF_ECC=0

Thanks & Regards
Raju S

[Abbas]

Hi Raju,

I appreciate your comment, but it does not assist me in solving this problem.

You can see that all the parameters are set before the make_all command and that when we check to make sure their values are valid, as shown in the figure below, they are set correctly.

I acknowledge your assistance and reply. Please advise me on a better solution to this issue.

Abbas Ali
FPGA Engineer

[Raju]

Hi Abbas Ali,

Thanks for the reply.

Can you try once again the steps in below way
1)export LM_LICENSE_FILE= /home/ubuntu/LR-122.dat(Your License Path)
2)Download the startix 10 ghrd file
3)export QUARTUS_DEVICE=1SX280LU2F50E2VG
4)export FPGA_device=1SX280LU2F50E2VG
5)export HPS_ENABLE_SGMII=0
6)export ENABLE_PARTIAL_RECONFIGURATION=0
7)export ENABLE_NIOSV_SUBSYS=0
8)export ENABLE_HPS_EMIF_ECC=0
9)invoke the nios2 shell
10)make scrub_clean_all
11)make generate_from_tcl
12)make all

Restart the system and try above mentioned steps in root user mode.
Hope this should work.

Thanks & Regards
Raju S

[Abbas]

Hi Raju,

Thank you for your most recent response, which was really useful. Without making a single mistake, we were able to successfully build the Stratix 10 SoC GSRD up to Build Yocto.

bitbake_image
Gather files:
package

Thank you for staying in touch with us to assist us as soon as you can in building our Strartix 10 SoC GSRD. We are moving to the next stage i.e. application to read any HSP-to-FPGA Bridges or the MPU address space. So, to read a 32-bit register for the entire MPU (HPS) memory space. If you have any related forums then share the link with me, I will also go through it for any guidance.

Let’s stay in touch if we face any problems, then we will let you know. Thanks

Abbas Ali
FPGA Engineer

[Raju]

Hi Abbas Ali,

Thanks for the response.

May i know, is it software application to just read /write ?

The below link for the reference

Hardware Library (HWLibs) | Documentation | RocketBoards.org

Thanks & Regards
Raju S